Chisel

Fame1FPGABackend

class Fame1FPGABackend extends FPGABackend with Fame1Transform

Linear Supertypes
Fame1Transform, FPGABackend, VerilogBackend, Backend, AnyRef, Any
Ordering
  1. Alphabetic
  2. By inheritance
Inherited
  1. Fame1FPGABackend
  2. Fame1Transform
  3. FPGABackend
  4. VerilogBackend
  5. Backend
  6. AnyRef
  7. Any
  1. Hide All
  2. Show all
Learn more about member selection
Visibility
  1. Public
  2. All

Instance Constructors

  1. new Fame1FPGABackend()

Value Members

  1. final def !=(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  2. final def !=(arg0: Any): Boolean

    Definition Classes
    Any

  3. final def ##(): Int

    Definition Classes
    AnyRef → Any

  4. final def ==(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  5. final def ==(arg0: Any): Boolean

    Definition Classes
    Any

  6. val analyses: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes
    Backend

  7. final def asInstanceOf[T0]: T0

    Definition Classes
    Any

  8. def asValidName(name: String): String

    Definition Classes
    Backend

  9. def assignClockAndResetToModules: Unit

    Definition Classes
    Backend

  10. def backannotationAnalyses: Unit

    Definition Classes
    Backend

  11. def backannotationTransforms: Unit

    Definition Classes
    Backend

  12. def checkPorts(topC: Module): Unit

    Definition Classes
    Backend

  13. def clone(): AnyRef

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  14. def collectNodesIntoComp(dfsStack: Stack[Node]): Unit

    Definition Classes
    Backend

  15. val compIndices: HashMap[String, Int]

    Definition Classes
    VerilogBackend

  16. def compile(c: Module, flags: String): Unit

    Definition Classes
    VerilogBackend → Backend

  17. def connectResets: Unit

    Definition Classes
    Backend

  18. def createClkDomain(root: Node, walked: ArrayBuffer[Node]): Unit

    Definition Classes
    Backend

  19. def createOutputFile(name: String): FileWriter

    Definition Classes
    Backend

  20. def depthString(depth: Int): String

    Definition Classes
    Backend

  21. def doCompile(top: Module, out: FileWriter, depth: Int): Unit

    Definition Classes
    VerilogBackend

  22. def elaborate(c: Module): Unit

    Definition Classes
    VerilogBackend → Backend

  23. def emitAssert(a: Assert): String

    Definition Classes
    VerilogBackend

  24. def emitChildren(top: Module, defs: HashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

    Definition Classes
    VerilogBackend

  25. def emitDec(node: Node): String

    Definition Classes
    FPGABackend → VerilogBackend → Backend

  26. def emitDecBase(node: Node): String

    Definition Classes
    VerilogBackend

  27. def emitDecs(c: Module): StringBuilder

    Definition Classes
    VerilogBackend

  28. def emitDef(node: Node): String

    Definition Classes
    FPGABackend → VerilogBackend → Backend

  29. def emitDef(c: Module): String

    Definition Classes
    VerilogBackend

  30. def emitDefs(c: Module): StringBuilder

    Definition Classes
    VerilogBackend

  31. def emitInit(node: Node): String

    Definition Classes
    VerilogBackend

  32. def emitInits(c: Module): StringBuilder

    Definition Classes
    VerilogBackend

  33. def emitModuleText(c: Module): String

    Definition Classes
    VerilogBackend

  34. def emitPortDef(m: MemAccess, idx: Int): String

    Definition Classes
    VerilogBackend

  35. def emitPrintf(p: Printf): String

    Definition Classes
    VerilogBackend

  36. def emitRef(node: Node): String

    Definition Classes
    VerilogBackend → Backend

  37. def emitRef(c: Module): String

    Definition Classes
    Backend

  38. def emitReg(node: Node): String

    Definition Classes
    FPGABackend → VerilogBackend

  39. def emitRegs(c: Module): StringBuilder

    Definition Classes
    VerilogBackend

  40. def emitTmp(node: Node): String

    Definition Classes
    VerilogBackend → Backend

  41. def emitWidth(node: Node): String

    Definition Classes
    VerilogBackend

  42. def ensureDir(dir: String): String

    Ensures a directory *dir* exists on the filesystem.

    Ensures a directory *dir* exists on the filesystem.

    Definition Classes
    Backend

  43. final def eq(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  44. def equals(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  45. def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

    Definition Classes
    Backend

  46. def extractClassName(comp: Module): String

    Definition Classes
    Backend

  47. def finalize(): Unit

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  48. def flushModules(out: FileWriter, defs: HashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

    Definition Classes
    VerilogBackend

  49. val flushedTexts: HashSet[String]

    Definition Classes
    VerilogBackend

  50. def fullyQualifiedName(m: Node): String

    Definition Classes
    Backend

  51. def gatherChildren(root: Module): ArrayBuffer[Module]

    Definition Classes
    Backend

  52. def gatherClocksAndResets: Unit

    Definition Classes
    Backend

  53. def genHarness(c: Module, name: String): Unit

    Definition Classes
    VerilogBackend

  54. def genIndent(x: Int): String

    Attributes
    protected
    Definition Classes
    Backend

  55. final def getClass(): Class[_]

    Definition Classes
    AnyRef → Any

  56. def getPseudoPath(c: Module, delim: String = "/"): String

    Definition Classes
    Backend

  57. def getSignalPathName(n: Node, delim: String = "/", isRealName: Boolean = false): String

    Definition Classes
    Backend

  58. def hashCode(): Int

    Definition Classes
    AnyRef → Any

  59. def initBackannotation: Unit

    Definition Classes
    Backend

  60. def initializeDFS: Stack[Node]

    Definition Classes
    Backend

  61. def isBitsIo(node: Node, dir: IODirection): Boolean

    Nodes which are created outside the execution trace from the toplevel component constructor (i.

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.

    This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Module.nodes and Node.component).

    We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.

    Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

    Definition Classes
    Backend

  62. final def isInstanceOf[T0]: Boolean

    Definition Classes
    Any

  63. def isMultiWrite(m: Mem[_]): Boolean

    Definition Classes
    FPGABackend

  64. val keywords: HashSet[String]

    Definition Classes
    VerilogBackend → Backend

  65. def levelChildren(root: Module): Unit

    Definition Classes
    Backend

  66. val memConfs: HashMap[String, String]

    Definition Classes
    VerilogBackend

  67. def nameAll(root: Module): Unit

    Definition Classes
    Backend

  68. def nameChildren(root: Module): Unit

    Definition Classes
    Backend

  69. def nameRsts: Unit

    Definition Classes
    Backend

  70. final def ne(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  71. final def notify(): Unit

    Definition Classes
    AnyRef

  72. final def notifyAll(): Unit

    Definition Classes
    AnyRef

  73. val preElaborateTransforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes
    Backend

  74. def printStack: Unit

    Prints the call stack of Component as seen by the push/pop runtime.

    Prints the call stack of Component as seen by the push/pop runtime.

    Attributes
    protected
    Definition Classes
    Backend

  75. def pruneNodes: Unit

    Definition Classes
    Backend

  76. def pruneUnconnectedIOs(m: Module): Unit

    Definition Classes
    Backend

  77. def romStyle: String

    Definition Classes
    FPGABackend → VerilogBackend

  78. def setPseudoNames(c: Module): Unit

    Definition Classes
    Backend

  79. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes
    AnyRef

  80. def toString(): String

    Definition Classes
    AnyRef → Any

  81. val transforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes
    Backend

  82. final def wait(): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  83. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  84. final def wait(arg0: Long): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  85. def writeMap(m: Mem[_], exclude: Int = 1): Seq[String]

    Definition Classes
    FPGABackend

  86. def writeOutGraph(c: Module): Unit

    Definition Classes
    Backend

  87. def writen(m: MemWrite): Int

    Definition Classes
    FPGABackend

Inherited from Fame1Transform

Inherited from FPGABackend

Inherited from VerilogBackend

Inherited from Backend

Inherited from AnyRef

Inherited from Any

Ungrouped