FPGABackend

Instance Constructors

new FPGABackend()

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def W0Wtransform(): Unit

Definition Classes
Backend
def addBindings: Unit

Definition Classes
Backend
def addClocksAndResets: Unit

Definition Classes
Backend
def addDefaultResets: Unit

Definition Classes
Backend
val analyses: ArrayBuffer[(Module) ⇒ Unit]

Definition Classes
Backend
final def asInstanceOf[T0]: T0

Definition Classes
Any
def asValidName(name: String): String

Definition Classes
Backend
def assignClockAndResetToModules: Unit

Definition Classes
Backend
def checkModuleResolution: Unit

Definition Classes
Backend
def checkPorts: Unit

Definition Classes
Backend
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
def collectNodesIntoComp(mod: Module): Unit

Definition Classes
Backend
val compIndices: HashMap[String, Int]

Definition Classes
VerilogBackend
def compile(c: Module, flags: String): Unit

Definition Classes
VerilogBackend → Backend
def computeMemPorts(mod: Module): Unit

Definition Classes
Backend
def connectResets: Unit

Definition Classes
Backend
def createOutputFile(name: String): FileWriter

Definition Classes
FileSystemUtilities
def depthString(depth: Int): String

Definition Classes
Backend
def doCompile(top: Module, out: FileWriter, depth: Int): Unit

Definition Classes
VerilogBackend
def elaborate(c: Module): Unit

Definition Classes
VerilogBackend → Backend
def emitAssert(a: Assert): String

Definition Classes
VerilogBackend
def emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

Definition Classes
VerilogBackend
def emitDec(node: Node): String

Definition Classes
VerilogBackend → Backend
def emitDecBase(node: Node, wire: String = "wire"): String

Definition Classes
VerilogBackend
def emitDecReg(node: Node): String

Definition Classes
VerilogBackend
def emitDecs(c: Module): StringBuilder

Definition Classes
VerilogBackend
def emitDef(node: Node): String

Definition Classes
VerilogBackend → Backend
def emitDef(c: Module): String

Definition Classes
VerilogBackend
def emitDefs(c: Module): StringBuilder

Definition Classes
VerilogBackend
def emitInit(node: Node): String

Definition Classes
VerilogBackend
def emitInits(c: Module): StringBuilder

Definition Classes
VerilogBackend
def emitModuleText(c: Module): String

Definition Classes
VerilogBackend
def emitPortDef(m: MemAccess, idx: Int): String

Definition Classes
VerilogBackend
def emitPrintf(p: Printf): String

Definition Classes
VerilogBackend
def emitRef(node: Node): String

Definition Classes
VerilogBackend → Backend
def emitRef(c: Module): String

Definition Classes
Backend
def emitReg(node: Node): String

Definition Classes
VerilogBackend
def emitRegs(c: Module): StringBuilder

Definition Classes
VerilogBackend
def emitTmp(node: Node): String

Definition Classes
VerilogBackend → Backend
def emitWidth(node: Node): String

Definition Classes
VerilogBackend
def ensureDir(dir: String): String

Ensures a directory *dir* exists on the filesystem.
Ensures a directory *dir* exists on the filesystem.

Definition Classes
FileSystemUtilities
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

Definition Classes
Backend
def extractClassName(comp: Module): String

Definition Classes
Backend
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
def findCombLoop: Unit

Definition Classes
Backend
def findConsumers(mod: Module): Unit

Definition Classes
Backend
def findGraphDims: (Int, Int, Int)

Definition Classes
Backend
def flattenAll: Unit

Definition Classes
Backend
def flushModules(out: FileWriter, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

Definition Classes
VerilogBackend
val flushedTexts: HashSet[String]

Definition Classes
VerilogBackend
def forceMatchingWidths: Unit

Definition Classes
Backend
def fullyQualifiedName(m: Node): String

Definition Classes
Backend
def gatherClocksAndResets: Unit

Definition Classes
Backend
def genHarness(c: Module, name: String): Unit

Definition Classes
VerilogBackend
def genIndent(x: Int): String

Attributes
protected
Definition Classes
Backend
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def harnessAPIs(mainClk: Clock, clocks: ListSet[Clock], resets: List[Bool]): String

Definition Classes
VerilogBackend
def harnessBase(mainClk: Clock, resets: List[Bool], scanNodes: Array[Bits], printNodes: Array[Bits]): String

Definition Classes
VerilogBackend
def hashCode(): Int

Definition Classes
AnyRef → Any
def inferAll(mod: Module): Int

Definition Classes
Backend
def isBitsIo(node: Node, dir: IODirection): Boolean

Nodes which are created outside the execution trace from the toplevel component constructor (i.e.
Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.
This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Driver.nodes and Node.component).
We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.
Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

Definition Classes
Backend
def isEmittingComponents: Boolean

Definition Classes
VerilogBackend → Backend
def isInObject(n: Node): Boolean

Definition Classes
Backend
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
val keywords: Set[String]

Definition Classes
VerilogBackend → Backend
def lowerNodes(mod: Module): Unit

Definition Classes
Backend
def markComponents: Unit

Definition Classes
Backend
val memConfs: HashMap[String, String]

Definition Classes
VerilogBackend
def nameAll(mod: Module): Unit

Definition Classes
Backend
def nameBindings: Unit

Definition Classes
Backend
def nameRsts: Unit

Definition Classes
Backend
val nameSpace: HashSet[String]

Definition Classes
Backend
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
val needsLowering: Set[String]

Definition Classes
VerilogBackend → Backend
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
def printStack: Unit

Prints the call stack of Component as seen by the push/pop runtime.
Prints the call stack of Component as seen by the push/pop runtime.

Attributes
protected
Definition Classes
Backend
def pruneUnconnectedIOs(m: Module): Unit

Definition Classes
Backend
def removeTypeNodes(mod: Module): Int

All classes inherited from Data are used to add type information and do not represent logic itself.
All classes inherited from Data are used to add type information and do not represent logic itself.

Definition Classes
Backend
def sortComponents: Unit

Definition Classes
Backend
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def synthesizeable(node: Node): Boolean

Definition Classes
VerilogBackend
def toString(): String

Definition Classes
AnyRef → Any
val transforms: ArrayBuffer[(Module) ⇒ Unit]

Definition Classes
Backend
def verifyAllMuxes: Unit

Definition Classes
Backend
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )

Related Doc: package Chisel

class FPGABackend extends VerilogBackend

Instance Constructors

new FPGABackend()

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def W0Wtransform(): Unit

def addBindings: Unit

def addClocksAndResets: Unit

def addDefaultResets: Unit

val analyses: ArrayBuffer[(Module) ⇒ Unit]

final def asInstanceOf[T0]: T0

def asValidName(name: String): String

def assignClockAndResetToModules: Unit

def checkModuleResolution: Unit

def checkPorts: Unit

def clone(): AnyRef

def collectNodesIntoComp(mod: Module): Unit

val compIndices: HashMap[String, Int]

def compile(c: Module, flags: String): Unit

def computeMemPorts(mod: Module): Unit

def connectResets: Unit

def createOutputFile(name: String): FileWriter

def depthString(depth: Int): String

def doCompile(top: Module, out: FileWriter, depth: Int): Unit

def elaborate(c: Module): Unit

def emitAssert(a: Assert): String

def emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

def emitDec(node: Node): String

def emitDecBase(node: Node, wire: String = "wire"): String

def emitDecReg(node: Node): String

def emitDecs(c: Module): StringBuilder

def emitDef(node: Node): String

def emitDef(c: Module): String

def emitDefs(c: Module): StringBuilder

def emitInit(node: Node): String

def emitInits(c: Module): StringBuilder

def emitModuleText(c: Module): String

def emitPortDef(m: MemAccess, idx: Int): String

def emitPrintf(p: Printf): String

def emitRef(node: Node): String

def emitRef(c: Module): String

def emitReg(node: Node): String

def emitRegs(c: Module): StringBuilder

def emitTmp(node: Node): String

def emitWidth(node: Node): String

def ensureDir(dir: String): String

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

def extractClassName(comp: Module): String

def finalize(): Unit

def findCombLoop: Unit

def findConsumers(mod: Module): Unit

def findGraphDims: (Int, Int, Int)

def flattenAll: Unit

def flushModules(out: FileWriter, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

val flushedTexts: HashSet[String]

def forceMatchingWidths: Unit

def fullyQualifiedName(m: Node): String

def gatherClocksAndResets: Unit

def genHarness(c: Module, name: String): Unit

def genIndent(x: Int): String

final def getClass(): Class[_]

def harnessAPIs(mainClk: Clock, clocks: ListSet[Clock], resets: List[Bool]): String

def harnessBase(mainClk: Clock, resets: List[Bool], scanNodes: Array[Bits], printNodes: Array[Bits]): String

def hashCode(): Int

def inferAll(mod: Module): Int

def isBitsIo(node: Node, dir: IODirection): Boolean

def isEmittingComponents: Boolean

def isInObject(n: Node): Boolean

final def isInstanceOf[T0]: Boolean

val keywords: Set[String]

def lowerNodes(mod: Module): Unit

def markComponents: Unit

val memConfs: HashMap[String, String]

def nameAll(mod: Module): Unit