Chisel

Reg

Related Docs: class Reg | package Chisel

object Reg

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  1. final def !=(arg0: Any): Boolean

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  2. final def ##(): Int

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  3. final def ==(arg0: Any): Boolean

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  4. def apply[T <: Data](outType: T): T

  5. def apply[T <: Data](outType: T = null, next: T = null, init: T = null, clock: Clock = null): T

    *type_out* defines the data type of the register when it is read.

    *type_out* defines the data type of the register when it is read. update* and *reset* define the update and reset values respectively.

  6. final def asInstanceOf[T0]: T0

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  7. def clone(): AnyRef

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  8. final def eq(arg0: AnyRef): Boolean

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  9. def equals(arg0: Any): Boolean

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  10. def finalize(): Unit

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  11. final def getClass(): Class[_]

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  12. def hashCode(): Int

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  13. final def isInstanceOf[T0]: Boolean

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  14. final def ne(arg0: AnyRef): Boolean

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  15. final def notify(): Unit

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  16. final def notifyAll(): Unit

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  17. def regMaxWidth(m: ⇒ Node): Width

  18. def regWidth(r: ⇒ Node): (⇒ Node) ⇒ Width

    Rule: if r is using an inferred width, then don't enforce a width.

    Rule: if r is using an inferred width, then don't enforce a width. If it is using a user inferred width, set the the width

    XXX Can't specify return type. There is a conflict. It is either (Node) => (Int) or Int depending which execution path you believe.

  19. def regWidth(w: ⇒ Width)(implicit d: DummyImplicit): (⇒ Node) ⇒ Width

  20. final def synchronized[T0](arg0: ⇒ T0): T0

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  21. def toString(): String

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  22. def validateGen[T <: Data](gen: ⇒ T): Unit

  23. final def wait(): Unit

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  24. final def wait(arg0: Long, arg1: Int): Unit

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  25. final def wait(arg0: Long): Unit

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