Fixed

final def !=(arg0: Any): Boolean

def ##[T <: Data](right: T): Fixed.this.type

Cat bits together to into a single data object with the width of both combined

def ##(b: Node): Node

The cat operator to combine two values

0x5 ## 0x3 => 0x53

final def ##(): Int

def %(b: Fixed): Fixed

This is just the modulo of the two fixed point bit representations changed into SInt and operated on

def %(b: Bits): Bits

def &(b: Bits): Fixed.this.type

Bitwise and

def *(b: Fixed): Fixed

Multiply increasing the Bit Width

def *(b: Bits): Bits

def *%(b: Fixed): Fixed

Multiply truncating the result to the same Fixed format

def *&(b: Fixed): Fixed

Multiply with one bit of rounding

def +(b: Fixed): Fixed

def +(b: Bits): Bits

def -(b: Fixed): Fixed

def -(b: Bits): Bits

def /(b: Fixed): Fixed

def /(b: Bits): Bits

def :=(that: Data): Unit

def <(b: Fixed): Bool

def <<(b: UInt): Fixed.this.type

Shift left operation

def <=(b: Fixed): Bool

def <>(src: Node): Unit

Connect I/O of modules with the same name

def =/=(that: BitPat): Bool

def =/=(b: Bits): Bool

not equal to

def =/=[T <: Data](right: T): Bool

final def ==(arg0: Any): Boolean

def ===(b: Fixed): Bool

def ===(that: BitPat): Bool

def ===[T <: Data](right: T): Bool

def >(b: Fixed): Bool

def >=(b: Fixed): Bool

def >>(b: UInt): Fixed

def W0Wtransform(): Unit

Eliminate any zero-width wires attached to this node

def ^(b: Bits): Fixed.this.type

Bitwise xor

def ^^(src: Node): Unit

val _id: Int

The unique id of this node

def _isComplementOf(x: Node): Boolean

def andR(): Bool

reduction and, and all bits together

final def apply(range: (Int, Int)): UInt

Extract a range of bits, inclusive from hi to lo

final def apply(hi: UInt, lo: UInt): UInt

Extract a range of bits, inclusive from hi to lo

final def apply(hi: Int, lo: Int): UInt

Extract a range of bits, inclusive from hi to lo

myBits = 0x5, myBits(1,0) => 0x3

final def apply(bit: UInt): Bool

Extract a single bit at position 'bit' as a Bool

final def apply(bit: Int): Bool

Extract a single Bool at index *bit*.

def apply(name: String): Data

def asDirectionless(): Fixed.this.type

Set this Bits instantiation to be neither of INPUT or OUTPUT

def asInput(): Fixed.this.type

Set this Bits instatiation to be an INPUT

final def asInstanceOf[T0]: T0

def asOutput(): Fixed.this.type

Set this Bits instatiation to be an OUTPUT

final def asSInt(): SInt

final def asTypeFor(node: Node): Fixed.this.type

assigns this instance as the data type for *node*.

final def asUInt(): UInt

def assign(src: Node): Unit

def bitSet(off: UInt, dat: UInt): Fixed.this.type

Set bit 'off' in data dat

def canCSE: Boolean

lazy val chiselName: String

var clock: Option[Clock]

The clock for this node

def clone(): Fixed.this.type

def cloneType(): Fixed.this.type

clone this Fixed instantiation

def colonEquals(that: Bits): Unit

Assignment operator

def colonEquals[T <: Data](that: Seq[T]): Unit

def colonEquals(that: Bundle): Unit

var comp: Option[proc]

def componentOf: Module

Get the module that this node is a part of or the top module if not assigned yet

val consumers: LinkedHashSet[Node]

nodes that consume one of my outputs

def create(dir: IODirection, width: Int): Unit

def dblLitValue: Double

Convert the node literal to a Double

def default: proc

def defaultMissing: Boolean

def defaultRequired: Boolean

var dir: IODirection

def doProcAssign(src: Node, cond: Bool): Unit

var driveRand: Boolean

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

Compare two nodes

def equalsForCSE(x: Node): Boolean

def error(b: Bits): Bits

Error shown when operation is not defined

def finalize(): Unit

def flatten: Array[(String, Bits)]

def flip(): Fixed.this.type

Change INPUT to OUTPUT and OUTPUT to INPUT

def floLitValue: Float

Convert the node literal to a Float

def forceMatchingWidths: Unit

Force the width of this nodes input to have the same width this if known if input node width is known force width of this node

var fractionalWidth: Int

def fromBits(b: Bits): Fixed.this.type

def fromInt(x: Int): Fixed.this.type

Create a Fixed representation from an Int

def fromNode(n: Node): Fixed.this.type

Convert a Node to a Fixed data type with the same fractional width as this instantiation

final def getClass(): Class[_]

def getFractionalWidth(): Int

def getNode: Node

def getWidth(): Int

def hashCode(): Int

def hashCodeForCSE: Int

def illegalAssignment(that: Any): Unit

def infer: Boolean

Called while we're walking the graph inferring the width of nodes.

def init(n: String, w: Int, ins: Node*): Node

Init the node and calculate its width and add inputs to the node

def init(n: String, widthFunc: (⇒ Node) ⇒ Width, ins: Node*): Node

Init the node and calculate its width and add inputs to the node

def initOf(n: String, widthfunc: (⇒ Node) ⇒ Width, ins: Seq[Node]): Node

Init the node and calculate its width and add inputs to the node

val inputs: ArrayBuffer[Node]

The inputs that this node depends on

def isDirectionless: Boolean

final def isInstanceOf[T0]: Boolean

def isIo: Boolean

def isIo_=(isIo: Boolean): Unit

final def isLit: Boolean

This function determines if a node is a literal, a fixed value

def isTopLevelIO: Boolean

var isTypeNode: Boolean

def isTypeOnly: Boolean

Chisel3 - type-only nodes (no data - no initialization or assignment) This is used to determine which nodes must be Wire() wrapped, and whether Wire() wrapping of the node is legal or not.

def isUsedByClockHi: Boolean

def isWired: Boolean

def isZeroWidth: Boolean

val line: StackTraceElement

The trace information for chisel for this node

def litOf: Literal

def litValue(default: BigInt = BigInt(-1)): BigInt

def matchWidth(w: Width): Node

def max(b: Fixed): Fixed

def maybeFlatten: Seq[Node]

Deprecated: Do not use

def min(b: Fixed): Fixed

var modified: Boolean

def muxes: Seq[Mux]

var name: String

Name of the instance.

def nameIt(path: String, isNamingIo: Boolean): Unit

name this node

var named: Boolean

named is used to indicate that name was set explicitly and should not be overriden

final def ne(arg0: AnyRef): Boolean

def needWidth(): Int

final def newBinaryOp(right: Bits, opName: String): Fixed.this.type

final def newLogicalOp(right: Bits, opName: String): Bool

final def newReductionOp(opName: String): Bool

final def newUnaryOp(opName: String): Fixed.this.type

def next: Node

def nextOpt: Option[Node]

final def notify(): Unit

final def notifyAll(): Unit

def orR(): Bool

reduction or, or all bits together

def params: Parameters

def printTree(writer: PrintStream, depth: Int = 4, indent: String = ""): Unit

Prints all members of a node and recursively its inputs up to a certain depth level This method is purely used for debugging

def procAssign(src: Node): Unit

var procAssigned: Boolean

var prune: Boolean

def replaceTree(newNode: Node): Unit

Replace the subtree starting from this node with the indicated replacement

def review(): Unit

Review a node for optimization possibilities if its children have been updated

def setDefault(src: Node): Unit

def setIsTypeNode: Unit

make this node a type node

def setIsWired(value: Boolean): Unit

def setName(n: String): Unit

Set the name of this module to the string 'n'

def setWidth(w: Int): Unit

Force the bit width of a node

final def synchronized[T0](arg0: ⇒ T0): T0

def toBits(): UInt

def toBool(): Bool

Try to convert this data to a Bool

def toBools: Vec[Bool]

Split up this bits instantiation to a Vec of Bools

lazy val toNode: Node

def toSInt(): SInt

def toString(): String

def toUInt(): UInt

def unary_-(): Fixed

def unary_~(): Fixed.this.type

invert all bits with ~

def usesInClockHi(i: Node): Boolean

def verifyMuxes: Unit

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

def xorR(): Bool

reduction xor, xor all bits together

def |(b: Bits): Fixed.this.type

Bitwise or

def !=(that: BitPat): Bool

def !=(b: Bits): Bool