DataRef
passes
DataRefMap
RemoveCHIRRTL
DeadCodeElimination
passes
transforms
Debug
LogLevel
DecInput
wiring
DecKind
wiring
DecOutput
wiring
DecWire
wiring
DeclarationNotFoundException
Utils
DedupModules
transforms
DefAnnotatedMemory
memlib
DefInstance
ir
DefInstanceGraphNode
altIR
DefMemory
ir
DefModule
ir
DefNode
ir
DefRegister
ir
DefWire
ir
DefWireGraphNode
altIR
Default
ir
Defaults
ExpandWhens
DeletedAnnotation
annotations
DiGraph
graph
Direction
ir
Div
PrimOps
DoPrim
ir
DontCheckCombLoopsAnnotation
transforms
DontTouchAnnotation
transforms
DontTouchNotFoundException
DontTouchAnnotation
DoubleParam
ir
Driver
firrtl
Dshl
PrimOps
DshlMaxWidth
CheckWidths
DshlTooBig
CheckWidths
Dshlw
firrtl
Dshr
PrimOps
dataType
DefMemory
DefAnnotatedMemory
debug
Logger
declare
VerilogRender
declares
VerilogRender
dedupInstances
DedupModules
deduplicate
DedupModules
default
InfoMap
defaultConnects
ReplaceMemMacros
defaultMaxCatLen
CombineCats
defaultMessage
FIRRTLException
defaultPortSeq
MemPortUtils
MemTransformUtils
defname
FIRRTLParser
ExtModule
delete
RenameMap
deleteDirectoryHierarchy
FileUtils
deletedAnnotations
CircuitState
delim
LowerTypes
depth
DefMemory
DefAnnotatedMemory
deserialize
JsonProtocol
deserializeTry
JsonProtocol
diff
Utils
dir
FIRRTLParser
dirName
TopWiringOutputFilesAnnotation
direction
CDefMPort
PortGraphNode
Port
doNotExitOnHelp
HasParser
dontCheckCombLoops
FirrtlExecutionOptions
dramaticError
Driver
dramaticWarning
Driver
dump
YamlFileWriter
duplicate
LegacyAnnotation
LoadMemoryAnnotation
SingleTargetAnnotation
InlineAnnotation
ClockListAnnotation
NoDedupMemAnnotation
SinkAnnotation
SourceAnnotation
BlackBoxInlineAnno
BlackBoxPathAnno
BlackBoxResourceAnno
DontTouchAnnotation
FlattenAnnotation
NoDedupAnnotation
OptimizableExtModuleAnnotation
TopWiringAnnotation
duplicateSubCircuitsFromAnno
Flatten