NameSet
CheckChirrtl
CheckHighForm
Named
annotations
NamedGraphNode
altIR
NamedSerializer
JsonProtocol
Namespace
firrtl
Neg
PrimOps
NegArgException
CheckHighForm
NegMemSizeException
CheckChirrtl
CheckHighForm
NegUIntException
CheckHighForm
NegVecSizeException
CheckChirrtl
CheckHighForm
NegWidthException
CheckChirrtl
CheckHighForm
CheckWidths
Neq
PrimOps
Netlist
ExpandWhens
InferReadWritePass
VerilogMemDelays
CombineCats
ReplaceTruncatingArithmetic
NoDCEAnnotation
transforms
NoDedupAnnotation
transforms
NoDedupMemAnnotation
memlib
NoInfo
ir
NoTargetAnnotation
annotations
NoTopModuleException
CheckChirrtl
CheckHighForm
NodeCount
analyses
NodeKind
firrtl
NodeMap
Utils
ExpandWhens
NodePassiveType
CheckTypes
None
LogLevel
Not
PrimOps
NotUniqueException
CheckChirrtl
CheckHighForm
nWords
VRandom
name
CDefMPort
CDefMemory
EmittedComponent
EmittedFirrtlCircuit
EmittedFirrtlModule
EmittedVerilogCircuit
EmittedVerilogModule
Transform
VarWidth
WDefInstance
WDefInstanceConnector
WRef
WSubField
DefInstanceGraphNode
DefWireGraphNode
NamedGraphNode
PortGraphNode
ReferenceGraphNode
SubFieldGraphNode
CircuitName
ComponentName
ModuleName
DefInstance
DefMemory
DefModule
DefNode
DefRegister
DefWire
DoubleParam
ExtModule
Field
HasName
IntParam
Module
Param
Port
RawStringParam
Reference
StringParam
SubField
MPort
DefAnnotatedMemory
Pin
Source
Top
Lineage
BlackBoxInlineAnno
namedNode
ReferenceGraphNode
namespace
VerilogRender
ModuleNamespaceAnnotation
neighbors
AssignableGraphNode
ConnectGraphNode
FirrtlGraphNode
IsInvalidGraphNode
ReferenceGraphNode
SubFieldGraphNode
SubIndexGraphNode
netlist
VerilogRender
newInstance
GroupAnnotation
newModule
GroupAnnotation
newName
Namespace
newTemp
Namespace
nextToken
LexerHelper
FIRRTLLexer
niceName
Utils
noDCE
FirrtlExecutionOptions
node
CyclicException
nodes
ModuleGraph
nonequivalent
NodeCount