SIntLiteral
ir
SIntType
ir
SIntZero
RemoveValidIf
SeqMemSet
RemoveCHIRRTL
SeqTransform
firrtl
SeqTransformBased
firrtl
SerializedComponentName
AnnotationUtils
SerializedModuleName
AnnotationUtils
Shl
PrimOps
Shlw
firrtl
Shr
PrimOps
Simlist
ExpandWhens
SimpleMidTransform
memlib
SimpleTransform
memlib
SingleFile
firrtl
SingleStringAnnotation
annotations
SingleTargetAnnotation
annotations
SinkAnnotation
wiring
Source
memlib
SourceAnnotation
wiring
SplitExpressions
passes
Statement
ir
StatementGraphNode
altIR
Statements
InferReadWritePass
StmtMap
Mappers
Stop
ir
StringLit
ir
StringParam
ir
Sub
PrimOps
SubAccess
ir
SubField
ir
SubFieldGraphNode
altIR
SubIndex
ir
SubIndexGraphNode
altIR
SubfieldNotInBundle
CheckTypes
SubfieldOnNonBundle
CheckTypes
Subw
firrtl
SyntaxErrorsException
firrtl
SystemVerilogCompiler
firrtl
sempred
FIRRTLParser
separator
YamlFileWriter
seq
CDefMemory
seqCat
firrtl
seqToAnnoSeq
firrtl
serialize
CDefMPort CDefMemory EmptyExpression ExpWidth MInfer MRead MReadWrite MWrite MaxWidth MinWidth MinusWidth PlusWidth RenameMap VRandom VarWidth WDefInstance WDefInstanceConnector WInvalid WRef WSubAccess WSubField WSubIndex WVoid Annotation CircuitName ComponentName DeletedAnnotation JsonProtocol LegacyAnnotation ModuleName Named AnalogType Attach Block BundleType Circuit ClockType Conditionally Connect DefInstance DefMemory DefNode DefRegister DefWire Default DoPrim DoubleParam EmptyStmt ExtModule Field FirrtlNode FixedLiteral FixedType Flip Info Input IntParam IntWidth IsInvalid Module Mux Output Param PartialConnect Port PrimOp Print RawStringParam Reference SIntLiteral SIntType Stop StringLit StringParam SubAccess SubField SubIndex UIntLiteral UIntType UnknownType UnknownWidth ValidIf VectorType ConfWriter DefAnnotatedMemory Lineage Modifications BlackBoxInlineAnno BlackBoxPathAnno BlackBoxResourceAnno BlackBoxTargetDirAnno Ledger Ledger
serializeHeader
DefModule
serializeTry
JsonProtocol
setCircuit
RenameMap
setClassLogLevels
Logger
setConsole
Logger
setLevel
Logger
setModule
RenameMap
setModuleName
Ledger Ledger
setOptions
Logger
setOutput
Logger
setTargetDirName
ExecutionOptionsManager
setTopName
ExecutionOptionsManager
setTopNameIfNotSet
ExecutionOptionsManager
set_mdir_s
CInferMDir
set_primop_type
PrimOps
sharedParent
Lineage
shortSerialize
Lineage
showUsageAsError
ExecutionOptionsManager
simple_reset
FIRRTLParser
simple_reset0
FIRRTLParser
simple_stmt
FIRRTLParser
simplify
DiGraph FoldADD FoldAND FoldCommutativeOp FoldEqual FoldNotEqual FoldOR FoldXOR
simulate
VerilogRender
simulates
VerilogRender
sink
Lineage CombinationalPath
sinkParent
Lineage
sinks
WiringInfo WiringNames
sinksToSources
WiringUtils
size
CDefMemory VectorType
solve_constraints
InferWidths
source
Config Lineage WiringInfo WiringNames
sourceParent
Lineage
sources
CombinationalPath
splitRef
Utils
squashEmpty
Utils
st
CheckTypes
stmt
FIRRTLParser
stmtToType
Uniquify
stmts
Block
stop
VerilogRender
str
FIRRTLException
string
Print StringLit
stringify
VerilogEmitter
sub_type
Utils
subgraph
DiGraph
suffix
LoadMemoryAnnotation
suite
FIRRTLParser
swap
Utils