PLUS
PrimOps
Pad
PrimOps
PadDoPrimGen
ExprGen
PadWidths
passes
Param
ir
ParameterNotSpecifiedException
firrtl
ParameterRedefinedException
firrtl
Parser
firrtl
ParserException
firrtl
PartialConnect
ir
Pass
passes
PassBenchmark
hot
PassCircuitName
memlib
PassConfigUtil
memlib
PassException
passes
PassExceptions
passes
PassModuleName
memlib
PassOption
memlib
PassOptionMap
PassConfigUtil
PathNotFoundException
graph
Phase
options
PhaseDependency
PhaseManager
PhaseException
options
PhaseManager
options
PhasePrerequisiteException
options
Pin
memlib
PinAnnotation
memlib
PoisonKind
firrtl
PoisonWithFlipException
CheckHighFormLike
Port
ir
PortEmissionOption
firrtl
PortEmissionOptionDefault
firrtl
PortKind
firrtl
PortMap
Mappers
PortSerializer
JsonProtocol
PortSet
InferReadWritePass
PredNotUInt
CheckTypes
PreservesAll
options
PresetAnnotation
annotations
PrettyCharSet
DependencyManagerUtils
PrettyNoExprInlining
stage
PrimOp
ir
PrimOps
firrtl
Print
ir
PrintfArgNotGround
CheckTypes
ProgramArgsAnnotation
options
PropagatePresetAnnotations
transforms
ProtoBufEmitter
proto
ProtoBufSerialization
Annotation
PullMuxes
passes
p1
PrimOps
p2
PrimOps
pad
ConstantPropagation
parameter
FIRRTLParser
params
SingleExpressionCircuitGenerator
ExtModule
parentModule
GenericTarget
parse
ExecutionOptionsManager
Parser
DuplicateHandling
Shell
ClockListAnnotation
ReplSeqMemAnnotation
YamlFileReader
parseCharStream
Parser
parseDefModule
Parser
parseExpression
Parser
parseFile
Parser
parseInfo
Parser
parsePort
Parser
parseStatement
Parser
parseString
Parser
parseType
Parser
parser
HasParser
Shell
passSeq
ClockListTransform
passes
firrtl
path
ConnectionGraph
CircuitTarget
GenericTarget
InstanceTarget
IsMember
ModuleTarget
ReferenceTarget
Target
DiGraph
BlackBoxPathAnno
pathAsTargets
IsMember
pathExists
ModuleGraph
pathTarget
IsComponent
IsMember
ModuleTarget
pathlessTarget
InstanceTarget
IsMember
ModuleTarget
ReferenceTarget
pathsInDAG
ConnectionGraph
DiGraph
payload
WithValid
phase
FirrtlStage
phases
options
stage
logger
pin
Config
SinkAnnotation
SourceAnnotation
WiringInfo
WiringNames
pins
PinAnnotation
pipelineWithValid
MemDelayAndReadwriteTransformer
point
FixedLiteral
FixedType
IntervalType
port
FIRRTLParser
portCons
WDefInstanceConnector
portdefs
VerilogRender
ports
IRLookup
DefModule
ExtModule
Module
MemConf
pow
IsKnown
Closed
Open
pow_minus_one
Utils
preState
PassBenchmark
TransformBenchmark
pred
Conditionally
Verification
prefix
LoadMemoryAnnotation
TopWiringAnnotation
prepare
ResolvedAnnotationPaths
prerequisites
AddDescriptionNodes
DependencyAPIMigration
MinimumHighFirrtlEmitter
MinimumVerilogEmitter
SystemVerilogEmitter
Transform
VerilogEmitter
GetNamespace
CleanupNamedTargets
EliminateTargetPaths
FirrtlToTransitionSystem
StutteringClockTransform
ProtoBufEmitter
CheckResets
DependencyAPI
DependencyManager
AddDefaults
Checks
ConvertLegacyAnnotations
DeletedWrapper
GetIncludes
WriteOutputAnnotations
CInferMDir
CInferTypes
CheckChirrtl
CheckFlows
CheckHighForm
CheckInitialization
CheckTypes
CheckWidths
CommonSubexpressionElimination
ConvertFixedToSInt
ExpandConnects
ExpandWhens
ExpandWhensAndCheck
InferBinaryPoints
InferTypes
InferWidths
InlineInstances
Legalize
LowerTypes
PadWidths
PullMuxes
RemoveAccesses
RemoveCHIRRTL
RemoveEmpty
RemoveIntervals
RemoveValidIf
ReplaceAccesses
ResolveFlows
ResolveKinds
SplitExpressions
ToWorkingIR
TrimIntervals
Uniquify
VerilogModulusCleanup
VerilogPrep
ZeroLengthVecs
ZeroWidth
ClockListTransform
CreateMemoryAnnotations
InferReadWrite
ReplSeqMem
ReplaceMemMacros
ResolveMemoryReference
VerilogMemDelays
WiringTransform
FirrtlStage
AddCircuit
AddDefaults
AddImplicitEmitter
AddImplicitOutputFile
CatchExceptions
Checks
Compiler
AddImplicitAnnotationFile
AddImplicitEmitter
AddImplicitFirrtlFile
AddImplicitOutputFile
WriteEmitted
WrappedTransform
BlackBoxSourceHelper
CheckCombLoops
CombineCats
ConstantPropagation
DeadCodeElimination
DedupAnnotationsTransform
DedupModules
FixAddingNegativeLiterals
Flatten
FlattenRegUpdate
GroupComponents
InferResets
InlineBitExtractionsTransform
InlineBooleanExpressions
InlineCastsTransform
LegalizeAndReductionsTransform
LegalizeClocksAndAsyncResetsTransform
ManipulateNames
MustDeduplicateTransform
PropagatePresetAnnotations
RemoveReset
RemoveWires
RenameModules
ReplaceTruncatingArithmetic
SimplifyMems
SortModules
TopWiringTransform
VerilogRename
AssertSubmoduleAssumptions
ConvertAsserts
RemoveVerificationStatements
Checks
prettyPrint
Target
DependencyManager
prettyPrintRec
DependencyManager
prettyToString
CircuitGraph
prettyTree
DiGraph
primOp
DoPrimGen
primop
FIRRTLParser
printArgs
JQFReproOptions
printStream
OutputCaptor
printf
VerilogRender
productArity
IntWidth
productElement
IntWidth
productPrefix
IntWidth
programArgs
CommonOptions
StageOptions
propagateType
Addw
Dshlw
Add
And
Andr
AsAsyncReset
AsClock
AsFixedPoint
AsInterval
AsSInt
AsUInt
Bits
Cat
Clip
Cvt
DecP
Div
Dshl
Dshr
Eq
Geq
Gt
Head
IncP
Leq
Lt
Mul
Neg
Neq
Not
Or
Orr
Pad
Rem
SetP
Shl
Shr
Squeeze
Sub
Tail
Wrap
Xor
Xorr
Subw
PrimOp
proto
backends
firrtl
pullToken
LexerHelper
pure
StateGen