class MinimumVerilogEmitter extends VerilogEmitter with Emitter
- Alphabetic
- By Inheritance
- MinimumVerilogEmitter
- VerilogEmitter
- Emitter
- SeqTransform
- SeqTransformBased
- Transform
- DependencyAPI
- TransformLike
- LazyLogging
- AnyRef
- Any
- Hide All
- Show All
- Public
- All
Instance Constructors
- new MinimumVerilogEmitter()
Type Members
-
class
VerilogRender extends AnyRef
Used by getRenderer, it has machinery to produce verilog from IR.
Used by getRenderer, it has machinery to produce verilog from IR. Making this a class allows access to particular parts of the verilog emission.
- Definition Classes
- VerilogEmitter
Value Members
-
final
def
!=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
final
def
##(): Int
- Definition Classes
- AnyRef → Any
-
final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
def
AND(e1: WrappedExpression, e2: WrappedExpression): Expression
- Definition Classes
- VerilogEmitter
-
def
addFormalStatement(formals: Map[Expression, ArrayBuffer[Seq[Any]]], clk: Expression, en: Expression, stmt: Seq[Any], info: Info, msg: StringLit): Unit
- Definition Classes
- VerilogEmitter
-
final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
-
def
clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native() @HotSpotIntrinsicCandidate()
-
def
emit(state: CircuitState, writer: Writer): Unit
- Definition Classes
- VerilogEmitter → Emitter
-
def
emit(x: Any, top: Int)(implicit w: Writer): Unit
- Definition Classes
- VerilogEmitter
-
def
emit(x: Any)(implicit w: Writer): Unit
- Definition Classes
- VerilogEmitter
-
final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
def
equals(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
def
execute(state: CircuitState): CircuitState
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
- state
Input Firrtl AST
- returns
A transformed Firrtl AST
- Definition Classes
- VerilogEmitter → SeqTransform → Transform
-
final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
def
getLogger: Logger
- Definition Classes
- LazyLogging
-
def
getRenderer(descriptions: Seq[DescriptionAnnotation], m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer): VerilogRender
Gets a reference to a verilog renderer.
Gets a reference to a verilog renderer. This is used by the current standard verilog emission process but allows access to individual portions, in particular, this function can be used to generate the header for a verilog file without generating anything else.
- descriptions
comments to be emitted
- m
the start module
- moduleMap
a way of finding other modules
- writer
where rendering will be placed
- returns
the render reference
- Definition Classes
- VerilogEmitter
-
def
getRenderer(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer): VerilogRender
Gets a reference to a verilog renderer.
Gets a reference to a verilog renderer. This is used by the current standard verilog emission process but allows access to individual portions, in particular, this function can be used to generate the header for a verilog file without generating anything else.
- m
the start module
- moduleMap
a way of finding other modules
- writer
where rendering will be placed
- returns
the render reference
- Definition Classes
- VerilogEmitter
-
def
hashCode(): Int
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
def
inputForm: LowForm.type
The firrtl.CircuitForm that this transform requires to operate on
The firrtl.CircuitForm that this transform requires to operate on
- Definition Classes
- VerilogEmitter → Transform
-
def
invalidates(a: Transform): Boolean
A function that, given *another* transform (parameter
a
) will return true if this transform invalidates/undos the effects of the *other* transform (parametera
).A function that, given *another* transform (parameter
a
) will return true if this transform invalidates/undos the effects of the *other* transform (parametera
).- a
transform
- Definition Classes
- Emitter → Transform → DependencyAPI
-
final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
-
val
logger: Logger
- Attributes
- protected
- Definition Classes
- LazyLogging
-
def
name: String
A convenience function useful for debugging and error messages
A convenience function useful for debugging and error messages
- Definition Classes
- Transform → TransformLike
-
final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
def
op_stream(doprim: DoPrim): Seq[Any]
- Definition Classes
- VerilogEmitter
-
def
optionalPrerequisiteOf: Seq[Nothing]
A sequence of transforms to add this transform as an
optionalPrerequisite
.A sequence of transforms to add this transform as an
optionalPrerequisite
. The use ofoptionalPrerequisiteOf
enables the transform declaring them to always run before some other transforms. However, declaringoptionalPrerequisiteOf
will not result in the sequence of transforms executing.This is useful for providing an ordering constraint to guarantee that other transforms (e.g., emitters) will not be scheduled before you.
- Definition Classes
- VerilogEmitter → Transform → DependencyAPI
- Note
This method **will not** result in the listed transforms running. If you want to add multiple transforms at once, you should use a
DependencyManager
with multiple targets.
-
def
optionalPrerequisites: Seq[Dependency[Transform]]
All transforms that, if a prerequisite of *another* transform, will run before this transform.
All transforms that, if a prerequisite of *another* transform, will run before this transform.
- Definition Classes
- Transform → DependencyAPI
- Note
The use of a Seq here is to preserve input order. Internally, this will be converted to a private, ordered Set.
-
def
outputForm: LowForm.type
The firrtl.CircuitForm that this transform outputs
The firrtl.CircuitForm that this transform outputs
- Definition Classes
- VerilogEmitter → Transform
-
val
outputSuffix: String
An output suffix to use if the output of this Emitter was written to a file
An output suffix to use if the output of this Emitter was written to a file
- Definition Classes
- VerilogEmitter → Emitter
-
def
prerequisites: Seq[Dependency[Transform]]
All transform that must run before this transform
All transform that must run before this transform
- Definition Classes
- MinimumVerilogEmitter → VerilogEmitter → Transform → DependencyAPI
- Note
The use of a Seq here is to preserve input order. Internally, this will be converted to a private, ordered Set.
-
def
remove_root(ex: Expression): Expression
- Definition Classes
- VerilogEmitter
-
final
def
runTransform(state: CircuitState): CircuitState
Perform the transform and update annotations.
Perform the transform and update annotations.
- state
Input Firrtl AST
- returns
A transformed Firrtl AST
- Definition Classes
- Transform
-
def
runTransforms(state: CircuitState): CircuitState
- Attributes
- protected
- Definition Classes
- SeqTransformBased
-
def
stringify(tpe: GroundType): String
- Definition Classes
- VerilogEmitter
-
def
stringify(param: Param): String
Turn Params into Verilog Strings
Turn Params into Verilog Strings
- Definition Classes
- VerilogEmitter
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
-
val
tab: String
- Definition Classes
- VerilogEmitter
-
def
toString(): String
- Definition Classes
- AnyRef → Any
-
def
transform(state: CircuitState): CircuitState
A mathematical transform on some type
A mathematical transform on some type
- returns
an output object of the same type
- Definition Classes
- Transform → TransformLike
-
def
transforms: Seq[Transform]
Preamble for every emitted Verilog file
Preamble for every emitted Verilog file
- Definition Classes
- MinimumVerilogEmitter → VerilogEmitter → SeqTransformBased
-
def
v_print(e: Expression, colNum: Int)(implicit w: Writer): Int
- Definition Classes
- VerilogEmitter
-
final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()
-
final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
def
wref(n: String, t: Type): WRef
- Definition Classes
- VerilogEmitter
Deprecated Value Members
-
def
dependents: Seq[Dependency[Transform]]
All transforms that must run after this transform
All transforms that must run after this transform
This is a means of prerequisite injection into some other transform. Normally a transform will define its own prerequisites. Dependents exist for two main situations:
First, they improve the composition of optional transforms. If some first transform is optional (e.g., an expensive validation check), you would like to be able to conditionally cause it to run. If it is listed as a prerequisite on some other, second transform then it must always run before that second transform. There's no way to turn it off. However, by listing the second transform as a dependent of the first transform, the first transform will only run (and be treated as a prerequisite of the second transform) if included in a list of target transforms that should be run.
Second, an external library would like to inject some first transform before a second transform inside FIRRTL. In this situation, the second transform cannot have any knowledge of external libraries. The use of a dependent here allows for prerequisite injection into FIRRTL proper.
- Definition Classes
- DependencyAPI
- Annotations
- @deprecated
- Deprecated
(Since version FIRRTL 1.3) Due to confusion, 'dependents' is being renamed to 'optionalPrerequisiteOf'. Override the latter instead.
- Note
The use of a Seq here is to preserve input order. Internally, this will be converted to a private, ordered Set.
- See also
firrtl.passes.CheckTypes for an example of an optional checking firrtl.Transform
-
def
finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( classOf[java.lang.Throwable] ) @Deprecated
- Deprecated
This is the documentation for Firrtl.