are all bits set
are all bits set
value to be and
reduced
result bit size
are all bits set
are all bits set
value to be and
reduced
result bit size
are all bits set
are all bits set
value to be and
reduced
result bit size
Implements an assigner that can be scheduled to publish clock transitions to specific black box implementations
Implements an assigner that can be scheduled to publish clock transitions to specific black box implementations
symbol name of instance
the instance
clock used by instance
source location
ClockInfo associates a clock with the given name and period and offset The period is in an arbitrary number of ticks.
ClockInfo associates a clock with the given name and period and offset The period is in an arbitrary number of ticks. The VCD logger currently sets these ticks to be nanosecond(ns). The first up transition takes place after initialOffset ticks. One or more clocks can be specified through the TreadleOptions clockInfo as a Seq of ClockInfo's or from string command line based --fint-clock-info or -fici which use the format clock-name[:period[:initial-offset] ]
the signal name of a clock
how many ticks between rising edges of this clock
the tick where the first up transition takes place.
Used internally by assigners that care about clock transitions
Used internally by assigners that care about clock transitions
the clock
the previous state of the clock
needed to get current and prev values
Creates a data store for the three underlying data types.
Creates a data store for the three underlying data types. The numberOfBuffers is used to control the ability to rollback execution. The meaning of the values of each slot must be maintained outside of this class. This class only supports (2 ** 31) - 1 of any ints, longs or bigs.
This class answers the question why does the given symbol have a particular value, it shows all arguments of PrimOPs and should only show any symbols value once.
This class answers the question why does the given symbol have a particular value, it shows all arguments of PrimOPs and should only show any symbols value once. Muxes only show the expanded derivation of the branch taken Display goes from top to bottom since it is usually the top value one wants to see that is rendered last.
Manage multiple top-level clocks step is interpreted here to mean advance to the next clock cycle considering all the clocks multiple clocks may fire at that time
are any bits set
are any bits set
value to be or
reduced
result bit size
are any bits set
are any bits set
value to be or
reduced
result bit size
are any bits set
are any bits set
value to be or
reduced
result bit size
A RollBackBuffer is the an image of DataStore at a particular time.
Manage the allocation of the rollback buffers
Maintains a ring buffer of dataStore images The only real complexity here is that the number of populated buffers is zero.
The scheduler holds the ordered assignment statements of the entire circuit.
The scheduler holds the ordered assignment statements of the entire circuit. Clocks have magic shadow symbols "clockName/prev". These shadows are used to make the circuit evaluation idempotent, i.e. evaluating the circuit at the moment of an positive clock transition can be done repeatedly and registers will only be advanced on the first call.
builds driving and driven by relationships between symbols
Created by chick on 4/21/16.
Controls whether a given memory cell should be logged to vcd output if logAllRadixOpt is defined then all indices for all memories should be logged otherwise if memory has an entry then check the memory index if the set contains -1 then all indices should be logged for that memory
are all bits set
are all bits set
value to be xor
reduced
result bit size
are all bits set
are all bits set
value to be xor
reduced
result bit size
are all bits set
are all bits set
value to be xor
reduced
result bit size
The default settings for a single clock are here.
The default settings for a single clock are here. Units are in arbitrary ticks
Provides three different aspects of the code necessary to create read and write register pipelines.
Provides three different aspects of the code necessary to create read and write register pipelines. The three cases are:
NOTE: See IMPORTANT NOTE above.