dfhdl-compiler-stages
dfhdl-compiler-stages
API
dfhdl
compiler
analysis
stages
verilog
VerilogBackend
VerilogPrinter
vhdl
VHDLBackend
VHDLPrinter
AddClkRst
BackendCompiler
BackendCompiler
CompiledDesign
ConnectClkRst
DFHDLUniqueNames
DropBAssignFromSeqProc
DropBinds
DropCondDcls
DropDesignDefs
DropLocalDcls
DropLocalDcls
DropUnreferencedAnons
DropUnreferencedVars
ExplicitClkRstCfg
ExplicitNamedVars
WhenHeader
ExplicitPrev
ExplicitRegInits
HasDB
HasDB
given_HasDB_DB
NameRegAliases
NameGroup
NamedAliases
Criteria
NamedAnonMultiref
NamedPrev
NamedSelection
Criteria
NamedAnonMultiref
NamedPrev
NamedSelection
OrderMembers
Order
Simple
Order
PrintCodeString
SanityCheck
SimpleOrderMembers
Stage
StageRunner
StageRunner
StagedDesign
StagedDesign
ToED
RegNet
ToRT
UniqueDesigns
VHDLProcToVerilog
ViaConnection
options
CompilerOptions
CompilerOptions
backends
dfhdl-compiler-stages
/
dfhdl
/
backends
backends
dfhdl.backends$
object
backends
Attributes
Graph
Reset zoom
Hide graph
Show graph
Supertypes
class
Object
trait
Matchable
class
Any
Self type
backends
.type
Members list
Clear all
Givens
Givens
given
verilog
:
verilog
given
vhdl
:
vhdl
In this article
Attributes
Members list
Givens
Givens