dfhdl-compiler-stages
dfhdl-compiler-stages
API
dfhdl
compiler
analysis
stages
verilog
VerilogBackend
VerilogDialect
VerilogPrinter
vhdl
DclScope
VHDLBackend
VHDLDialect
VHDLPrinter
AddClkRst
AddMagnets
BackendCompiler
BackendPrepStage
BreakOps
BreakOpsNoAssignments
BreakOpsWithAssignments
BundleStage
CompiledDesign
ConnectMagnets
DFHDLUniqueNames
DropBAssignFromSeqProc
DropBinds
DropDesignDefs
DropDomains
DropLocalDcls
DropMagnets
DropOpaques
DropOpaquesAll
DropOutportRead
DropProcessAll
DropUnreferencedAnons
DropUnreferencedVars
DropUserOpaques
ExplicitClkRstCfg
ExplicitNamedVars
WhenHeader
ExplicitRegInits
ExplicitState
GlobalizePortVectorParams
HasDB
HasDB
given_HasDB_DB
MatchToIf
NameRegAliases
NameGroup
NamedAnonCondExpr
NamedAnonMultiref
NamedPrev
NamedVerilogSelection
NoCheckStage
OrderMembers
Order
Simple
Order
PrintCodeString
SanityCheck
SimpleOrderMembers
SpecialControlStage
Stage
StageRunner
StageRunner
StagedDesign
StagedDesign
ToED
ToRT
UniqueDesigns
VHDLProcToVerilog
ViaConnection
options
CompilerOptions
CompilerOptions
Backend
CommitFolder
DropUserOpaques
LogLevel
NewFolderForTop
PrintBackendCode
PrintDFHDLCode
backends
verilog
vhdl
dfhdl-compiler-stages
/
dfhdl
/
dfhdl.options
/
CompilerOptions
/
PrintBackendCode
PrintBackendCode
dfhdl.options.CompilerOptions.PrintBackendCode
object
PrintBackendCode
Attributes
Graph
Reset zoom
Hide graph
Show graph
Supertypes
class
Object
trait
Matchable
class
Any
Self type
PrintBackendCode
.
type
Members list
Clear all
Givens
Givens
given
given_Conversion_Boolean_PrintBackendCode
:
Conversion
[
Boolean
,
PrintBackendCode
]
given
given_PrintBackendCode
:
PrintBackendCode
In this article
Attributes
Members list
Givens
Givens