Bool
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package core
Class used to write conditional operation on Data value
Class used to write conditional operation on Data value
val res = myBool ? myBits1 | myBits2
Class used to write conditional operation on Enumeration value
Class used to write conditional operation on Enumeration value
val res = myBool ? myEnum1 | myEnum2implicit conversion is used to send SpinalEnumElement
Concatenation between two signals
Concatenation between two signals
Hardware repeat count time a Bool
Bitwise AND operator
Hardware logical AND
Hardware logical AND
a Bool assign with the AND result
val result = myBool1 && myBool2
Standard hardware assignment, equivalent to <= in VHDL/Verilog
Standard hardware assignment, equivalent to <= in VHDL/Verilog
Automatic connection between two hardware signals or two bundles of the same type.
Automatic connection between two hardware signals or two bundles of the same type.
Direction is inferred by using signal direction (in/out). (Similar behavior to :=)
BitVector is not equal to MaskedLiteral
isNotEqualTo comparison between two SpinalHDL data
isNotEqualTo comparison between two SpinalHDL data
isEqualTo comparison between two SpinalHDL data
isEqualTo comparison between two SpinalHDL data
Conditional operation for Enumeration value
Conditional operation for Data value
Use as \= to have the same behavioral as VHDL variable
Use as \= to have the same behavioral as VHDL variable
Hardware logical XOR
Allow a signal of an io Bundle to be directionless.
Allow a signal of an io Bundle to be directionless.
Allow a signal to be overridden.
Allow a signal to be overridden.
Allow a register to be partially assigned
Allow a register to be partially assigned
Allow a register to have only an init (no assignments)
Allow a register to have only an init (no assignments)
Cast signal to Bits
Cast a Bool to an Bits of a given width
Cast a Bool to an Bits of a given width
the width of the Bits
a Bits data of a given length initialize to this
Set a signal as inout
Set a data as input
Set a data as output
Cast a Bool to an SInt
Cast a Bool to an SInt
a SInt data
mySInt := myBool.asSInt
Cast a Bool to an UInt of a given width
Cast a Bool to an UInt of a given width
the width of the UInt
an UInt data of a given length initialize to this
myUInt := myBool.asUInt(8 bits)
Cast a Bool to an UInt
Cast a Bool to an UInt
an UInt data
myUInt := myBool.asUInt
this is assigned to False
Set to False.
this is assigned to False when cond is True
Set a default value to a signal.
Set a default value to a signal.
Edge detection
Edge detection of this with an initial value
Edge detection of this with an initial value
the initial value
a Bool
val res = myBool.edge(False)
Edge detection without intial value
Detect all edges (falling, rising, toogling)
Detect all edges (falling, rising, toogling)
the initial value
a BoolEdges
val res = myBool.edges()
when(res.fall){...}
when(res.rise){...}
when(res.toggle){...}
Falling edge detection
Falling edge detection of this with an initial value
Falling edge detection of this with an initial value
the initial value
a Bool
val res = myBool.fall(False)
this is assigned to False when cond is True and the current value of this is True.
this is assigned to False when cond is True and the current value of this is True. see riseWhen()
Flip the direction of the signal.
Flip the direction of the signal.
in and out are swapped, inout stay the same.
For a register, get the value it will have at the next clock, as a combinational signal.
Return the width of the data
Get current component with all parents
Get current component with all parents
Create a signal set to 0
Does the base type have initial value
Does the base type have initial value
Set initial value of the signal
Set initial value of the signal
Is the baseType a node
Is the baseType a node
Is the basetype using reset signal
Is the basetype using reset signal
Is the basetype using soft reset signal
Is the basetype using soft reset signal
Check if the baseType is vital
Check if the baseType is vital
Use a SpinalHDL data as a selector for a mux.
Use a SpinalHDL data as a selector for a mux.
Version of SpinalHDL mux that allows Don't Care.
Version of SpinalHDL mux that allows Don't Care.
Use a scala.Seq of SpinalHDL data as mux inputs.
Use a scala.Seq of SpinalHDL data as mux inputs.
Use a scala.Seq of SpinalHDL data as mux inputs.
Use a scala.Seq of SpinalHDL data as mux inputs.
Version of SpinalHDL muxList that allows Don't Care.
Version of SpinalHDL muxList that allows Don't Care.
Put the combinatorial logic driving this signal in a separate process
Put the combinatorial logic driving this signal in a separate process
Disable combinatorial loop checking for this Data
Disable combinatorial loop checking for this Data
Pull a signal to the top level (use for debugging)
Pull a signal to the top level (use for debugging)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Remove all assignments of the base type
Return a version of the signal which is allowed to be automatically resized where needed.
Return a version of the signal which is allowed to be automatically resized where needed.
The resize operation is deferred until the point of assignment later. The resize may widen or truncate, retaining the LSB.
Rising edge detection
Rising edge detection of this with an initial value
Rising edge detection of this with an initial value
the initial value
a Bool
val res = myBool.rise(False)
this is assigned to True when cond is True and the current value of this is False.
this is assigned to True when cond is True and the current value of this is False. Useful for coding a simple boolean state machine. riseWhen() is typically paired with fallWhen() but also works together with setWhen() and clearWhen().
a Bool condition
this is rising when cond is True
val active = RegInit(False) riseWhen(request) fallWhen(acknowledge)
root interface
root interface
this is assigned to True
Set to True.
Set baseType to Combinatorial
Remove the direction (in, out, inout) to a signal
Set baseType to reg
Set baseType to Node
Set baseType to Node
Set the baseType to vital
Set the baseType to vital
Recursively set baseType to reg only for output
Recursively set baseType to reg only for output
this is assigned to True when cond is True
this is assigned to True when cond is True
a Bool condition
this is assigned to True when cond is True
myBool.setWhen(cond)
this is inverted when cond is True
this is inverted when cond is True
a Bool condition
this is inverted when cond is True
mybool.toggleWhen(request)
Hardware logical NOT
Hardware logical NOT
a Bool assign with the NOT result
val result = !myBool1
Hardware alternative to logical NOT
Hardware alternative to logical OR
Hardware logical OR
Hardware logical OR
a Bool assign with the OR result
val result = myBool1 || myBool2
(Since version ???) use setAsDirectionLess instead
(Since version ) see corresponding Javadoc for more information.
Generate this if condition is true
Generate this if condition is true
does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead
The
Booltype corresponds to a hardware boolean value (TrueorFalse)Bool Documentation