SInt
Related Doc:
package core
Used to know the data type of the children class of BitVector
Concatenation between two signals
Concatenation between two signals
Hardware modulo
Bitwise AND operator
Hardware multiplication
Hardware addition
Hardware safe addition with 1 bit expand
Hardware safe addition with saturation
Hardware subtraction
Hardware safe subtraction with 1 bit expand
Hardware safe subtraction with saturation
Hardware division
Assign a range value to a SInt
Assign a range value to a SInt
The first range value
Others range values
core.io.interrupt = (0 -> uartCtrl.io.interrupt, 1 -> timerCtrl.io.interrupt, default -> false)
Standard hardware assignment, equivalent to <= in VHDL/Verilog
Standard hardware assignment, equivalent to <= in VHDL/Verilog
Hardware "is less than right"
Logical shift Left (output width will increase of : w(this) + max(that) bits
Hardware arithmetic left shift (w(T) = w(this) + shift)
Hardware "is equal or less than right"
Automatic connection between two hardware signals or two bundles of the same type.
Automatic connection between two hardware signals or two bundles of the same type.
Direction is inferred by using signal direction (in/out). (Similar behavior to :=)
isNotEqualTo comparison between two SpinalHDL data
isNotEqualTo comparison between two SpinalHDL data
BitVector is not equal to MaskedLiteral
BitVector is not equal to MaskedLiteral
isEqualTo comparison between two SpinalHDL data
isEqualTo comparison between two SpinalHDL data
Compare a BitVector with a MaskedLiteral (M"110--0")
Compare a BitVector with a MaskedLiteral (M"110--0")
the maskedLiteral
a Bool data containing the result of the comparison
val myBool = myBits === M"0-1"
Hardware "is greater than right"
Hardware "is equal or greater than right"
Logical shift Right (output width == input width)
Hardware arithmetic right shift (w(T) = w(this) - shift)
Concatenation between a SInt and a Bool
Concatenation between a SInt and UInt
Concatenation between two SInt
Concatenation between two SInt
an SInt to append
a new SInt of width (width(this) + width(right))
val mySInt = sInt1 @@ sInt2
Use as \= to have the same behavioral as VHDL variable
Use as \= to have the same behavioral as VHDL variable
Bitwise XOR operator
Allow a signal of an io Bundle to be directionless.
Allow a signal of an io Bundle to be directionless.
Allow a signal to be overridden.
Allow a signal to be overridden.
Allow a register to be partially assigned
Allow a register to be partially assigned
Allow a register to have only an init (no assignments)
Allow a register to have only an init (no assignments)
Hardware logical AND of all bits
Hardware logical AND of all bits
Equivalent to this.asBits === ((BigInt(1) << getWidth) - 1).
Return a range of bits at offset and of width bitCount
Return a range of bits at offset and of width bitCount
Return the bit at index bitId
Return the bit at index bitId
Return a range of bits
Return a range of bits
val myBool = myBits(3 downto 1)
Cast signal to Bits
Return this.lsb
Return this.lsb
Cast the BitVector into a vector of Bool
Cast the BitVector into a vector of Bool
Set a signal as inout
Set a data as input
Set a data as output
Cast a SInt into an UInt
Cast a SInt into an UInt
a UInt data
myUInt := mySInt.asUInt
SInt ceil
lowest n bits Round Operation by BitCount
lowest n bits Round Operation by BitCount
SInt roundUp lowest m bits, friendly for hardware timing and area sign * ceil(abs(x))
Clear all bits
Set a default value to a signal.
Set a default value to a signal.
Drop lowest n bits
Drop lowest n bits
data10bits(9 downto 4)
val res = data10bits.drop(4)
Drop highest n bits
Drop highest n bits
data10bits(5 downto 0)
val res = data10bits.dropHigh(4)
Flip the direction of the signal.
Flip the direction of the signal.
in and out are swapped, inout stay the same.
return w(this)-n bits
SInt roundUp lowest m bits, friendly for hardware timing and area sign * floor(abs(x))
For a register, get the value it will have at the next clock, as a combinational signal.
Return the width of the data
Get current component with all parents
Get current component with all parents
Return the width
Return the width
Create a signal set to 0
Does the base type have initial value
Does the base type have initial value
Return the upper bound
Return the upper bound
Set initial value of the signal
Set initial value of the signal
Is the baseType a node
Is the baseType a node
Is the basetype using reset signal
Is the basetype using reset signal
Is the basetype using soft reset signal
Is the basetype using soft reset signal
Check if the baseType is vital
Check if the baseType is vital
Return the least significant bit
Return the least significant bit
Return the hardware maximum value between this and right
Return the hardware maximum value between this and right
Return the hardware minimum value between this and right
Return the hardware minimum value between this and right
Return the most significant bit
Return the most significant bit
Use a SpinalHDL data as a selector for a mux.
Use a SpinalHDL data as a selector for a mux.
Version of SpinalHDL mux that allows Don't Care.
Version of SpinalHDL mux that allows Don't Care.
Use a scala.Seq of SpinalHDL data as mux inputs.
Use a scala.Seq of SpinalHDL data as mux inputs.
Use a scala.Seq of SpinalHDL data as mux inputs.
Use a scala.Seq of SpinalHDL data as mux inputs.
Version of SpinalHDL muxList that allows Don't Care.
Version of SpinalHDL muxList that allows Don't Care.
Hardware logical NAND of all bits
Hardware logical NAND of all bits
Extract a range of bits of the BitVector
Extract a range of bits of the BitVector
Extract a range of bits of the BitVector
Extract a range of bits of the BitVector
Extract a bit of the BitVector
Extract a bit of the BitVector
Extract a bit of the BitVector
Extract a bit of the BitVector
Put the combinatorial logic driving this signal in a separate process
Put the combinatorial logic driving this signal in a separate process
Disable combinatorial loop checking for this Data
Disable combinatorial loop checking for this Data
Hardware logical NOR of all bits
Hardware logical NOR of all bits
Hardware logical NXOR of all bits
Hardware logical NXOR of all bits
Hardware logical OR of all bits
Hardware logical OR of all bits
Equivalent to this.asBits =/= 0.
Pull a signal to the top level (use for debugging)
Pull a signal to the top level (use for debugging)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Remove all assignments of the base type
Return a resized copy of x.
Return a resized copy of x.
Return a version of the signal which is allowed to be automatically resized where needed.
Return a version of the signal which is allowed to be automatically resized where needed.
The resize operation is deferred until the point of assignment later. The resize may widen or truncate, retaining the LSB.
root interface
root interface
Left rotation of that bits
Left rotation of that Bits
Left rotation of that Bits
Right rotation of that bits
Right rotation of that Bits
Right rotation of that Bits
SInt roundDown lowest m bits, complex for hardware , not recommended The algorithm represented by python code : ceil(x - 0.5)
SInt roundToInf sign * floor(abs(x) + 0.5)
SInt roundToZero The algorithm represented by python code : sign * ceil(abs(x) - 0.5)
SInt roundUp lowest m bits, friendly for hardware timing and area floor(x + 0.5)
Saturation highest m bits
Set all bits
Set all bits to value
Set all bits to value
Set all bits to value
Set all bits to value
Set baseType to Combinatorial
Remove the direction (in, out, inout) to a signal
Set baseType to reg
Set baseType to Node
Set baseType to Node
Set the baseType to vital
Set the baseType to vital
Recursively set baseType to reg only for output
Recursively set baseType to reg only for output
Set the width of the BitVector
Set the width of the BitVector
the width of the data
the BitVector of a given size
apart by a list of width
apart by a list of width
(List(A(1 downto 0), A(2 downto 4), A(9 downto 3))
val res = A.sliceBy(2, 3, 5) val res = A.sliceBy(List(2, 3, 5))
Split at n st bits
Split at n st bits
(data10bits(8 downto 4), data10bits(3 downto 0))
val res = data10bits.splitAt(4)
Split the BitVector into slice of x bits
Split the BitVector into slice of x bits
the width of the slice
allow subdivideIn to generate vectors with varying size
a Vector of slices
val res = myBits.subdivideIn(3 bits)
Split the BitVector into x slice
Split the BitVector into x slice
the width of the slice
allow subdivideIn to generate vectors with varying size
a Vector of slices
val res = myBits.subdivideIn(3 slices)
SInt symmetric
SInt symmetric
return a SInt which minValue equal -maxValue
val symmetrySInt = mySInt.symmetry
Take lowest n bits
Take lowest n bits
data10bits(3 downto 0)
val res = data10bits.take(4)
Take highest n bits
Take highest n bits
data10bits(9 downto 6)
val res = data10bits.takeHigh(4)
Discard the highest m bits
Negative number
Negative number
return a negative number
val result = -mySInt
Inverse bitwise operator
Hardware logical XOR of all bits
Hardware logical XOR of all bits
Equivalent to this.asBools.reduce(_ ^ _).
Bitwise OR operator
Logical shift left (output width == input width)
Logical shift left (output width == input width)
Logical shift Right (output width == input width)
Logical shift right (output width == input width)
Logical shift right (output width == input width)
the number of right shift
a Bits of width : w(this)
val result = myUInt |>> 4
(Since version ???) use setAsDirectionLess instead
(Since version ) see corresponding Javadoc for more information.
Generate this if condition is true
Generate this if condition is true
does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead
Return the range
Return the range
Use bitsRange instead
The
SInttype corresponds to a vector of bits that can be used for signed integer arithmetic.UInt/SIntDocumentation]]