Packages

c

spinal.core.internals

PhaseVerilog

class PhaseVerilog extends PhaseMisc with VerilogBase

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  2. By Inheritance
Inherited
  1. PhaseVerilog
  2. VerilogBase
  3. VhdlVerilogBase
  4. PhaseMisc
  5. Phase
  6. AnyRef
  7. Any
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new PhaseVerilog(pc: PhaseContext, report: SpinalReport[_])

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. val allocateAlgoIncrementaleBase: Int
  5. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  6. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
  7. def compile(component: Component): () => String
  8. def emitClockEdge(clock: String, edgeKind: EdgeKind): String
    Definition Classes
    VerilogBase
  9. def emitCommentAttributes(attributes: Iterable[Attribute]): String
    Definition Classes
    VerilogBase
  10. def emitDirection(baseType: BaseType): String
    Definition Classes
    VerilogBase
  11. def emitEnumLiteral[T <: SpinalEnum](senum: SpinalEnumElement[T], encoding: SpinalEnumEncoding, prefix: String = "`"): String
    Definition Classes
    VerilogBase
  12. def emitEnumPackage(out: FileWriter): Unit
  13. def emitEnumType(senum: SpinalEnum, encoding: SpinalEnumEncoding, prefix: String = "`"): String
    Definition Classes
    VerilogBase
  14. def emitEnumType[T <: SpinalEnum](senum: SpinalEnumCraft[T], prefix: String): String
    Definition Classes
    VerilogBase
  15. def emitExpressionWrap(e: Expression, name: String, nature: String): String
    Definition Classes
    VerilogBase
  16. def emitExpressionWrap(e: Expression, name: String): String
    Definition Classes
    VerilogBase
  17. def emitFunctions(component: Component, ret: StringBuilder): Unit
  18. def emitRange(node: WidthProvider): String
    Definition Classes
    VerilogBase
  19. def emitResetEdge(reset: String, polarity: Polarity): String
    Definition Classes
    VerilogBase
  20. def emitStructType(struct: SpinalStruct): String
    Definition Classes
    VerilogBase
  21. def emitSyntaxAttributes(attributes: Iterable[Attribute]): String
    Definition Classes
    VerilogBase
  22. def emitType(e: Expression): String
    Definition Classes
    VerilogBase
  23. val emitedComponent: Map[ComponentEmitterTrace, Component]
  24. val emitedComponentRef: ConcurrentHashMap[Component, Component]
  25. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  26. def equals(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef → Any
  27. def expressionAlign(net: String, section: String, name: String): String
    Definition Classes
    VerilogBase
  28. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  29. def getReEncodingFuntion(spinalEnum: SpinalEnum, source: SpinalEnumEncoding, target: SpinalEnumEncoding): String
    Definition Classes
    VerilogBase
  30. val globalPrefix: String
    Definition Classes
    VerilogBase
  31. def hasNetlistImpact: Boolean
    Definition Classes
    PhaseMiscPhase
  32. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  33. def impl(pc: PhaseContext): Unit
    Definition Classes
    PhaseVerilogPhase
  34. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  35. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  36. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  37. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  38. var outFile: FileWriter
  39. val romCache: HashMap[String, String]
  40. def rtlName: String
  41. def signalNeedProcess(baseType: BaseType): Boolean
    Definition Classes
    VerilogBase
  42. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  43. def targetPath: String
  44. val theme: Tab2
    Definition Classes
    VerilogBase
  45. def toString(): String
    Definition Classes
    AnyRef → Any
  46. val usedDefinitionNames: HashSet[String]
  47. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  48. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException]) @native()
  49. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable]) @Deprecated
    Deprecated

Inherited from VerilogBase

Inherited from VhdlVerilogBase

Inherited from PhaseMisc

Inherited from Phase

Inherited from AnyRef

Inherited from Any

Ungrouped