abstract class OrderedDecoupledHWIOTester extends HWIOTester

Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported. Testers that subclass this will be strictly ordered. Input will flow into their devices asynchronously but in order they were generated be compared in the order they are generated

Source
OrderedDecoupledHWIOTester.scala
Example:
  1. class XTimesXTester extends [[OrderedDecoupledHWIOTester]] {
      val device_under_test = new XTimesY
      test_block {
        for {
          i <- 0 to 10
          j <- 0 to 10
        } {
          input_event(device_under_test.io.in.x -> i, device_under_test.in.y -> j)
          output_event(device_under_test.io.out.z -> i*j)
        }
      }
    }

    an input event is a series of values that will be gated into the decoupled input interface at the same time an output event is a series of values that will be tested at the same time independent small state machines are set up for input and output interface all inputs regardless of interfaces are submitted to the device under test in the order in which they were created likewise, all outputs regardless of which interface are tested in the same order that they were created

Linear Supertypes
HWIOTester, BasicTester, Module, RawModule, BaseModule, IsInstantiable, HasId, internal.InstanceId, AnyRef, Any
Type Hierarchy
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. OrderedDecoupledHWIOTester
  2. HWIOTester
  3. BasicTester
  4. Module
  5. RawModule
  6. BaseModule
  7. IsInstantiable
  8. HasId
  9. InstanceId
  10. AnyRef
  11. Any
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new OrderedDecoupledHWIOTester()

Type Members

  1. class GlobalEventCounter extends AnyRef
  2. case class TestingEvent(port_values: Map[Data, BigInt], event_number: Int) extends Product with Serializable

Abstract Value Members

  1. abstract val device_under_test: Module
    Definition Classes
    HWIOTester

Concrete Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  9. def checkAndGetCommonDecoupledOrValidParentPort(pokes: Seq[(Data, BigInt)], must_be_decoupled: Boolean = true, event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

    Validate that all pokes ports are members of the same DecoupledIO makes a list of all decoupled parents based on the ports referenced in pokes

  10. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  11. final val clock: Clock
    Definition Classes
    Module
  12. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
  13. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  14. def computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]
    Definition Classes
    HasId
  15. val control_port_to_input_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]
  16. val decoupled_control_port_to_output_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]
  17. def desiredName: String
    Definition Classes
    BaseModule
  18. var enable_all_debug: Boolean
    Definition Classes
    HWIOTester
  19. var enable_printf_debug: Boolean
    Definition Classes
    HWIOTester
  20. var enable_scala_debug: Boolean
    Definition Classes
    HWIOTester
  21. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  22. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  23. def finish(): Unit

    this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid

    this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid

    Definition Classes
    OrderedDecoupledHWIOTesterHWIOTester → BasicTester
  24. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  25. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  26. def getCommonValidParentPort(expects: Seq[(Data, BigInt)], event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

    Validate that all pokes ports are members of the same DecoupledIO or ValidIO makes a list of all decoupled parents based on the ports referenced in pokes

  27. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  28. def hasSeed: Boolean
    Definition Classes
    HasId
  29. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  30. def inputEvent(pokes: (Data, BigInt)*): Unit
  31. val input_event_list: ArrayBuffer[Seq[(Data, BigInt)]]
  32. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  33. val io: Bundle
    Definition Classes
    BasicTester
  34. var io_info: IOAccessor
    Definition Classes
    HWIOTester
  35. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  36. def logPrintfDebug(fmt: String, args: Bits*): Unit
    Definition Classes
    HWIOTester
  37. def logScalaDebug(msg: => String): Unit
    Definition Classes
    HWIOTester
  38. final lazy val name: String
    Definition Classes
    BaseModule
  39. def nameIds(rootClass: Class[_]): HashMap[HasId, String]
    Attributes
    protected
    Definition Classes
    BaseModule
  40. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  41. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  42. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  43. def outputEvent(expects: (Data, BigInt)*): Unit
  44. val output_event_list: ArrayBuffer[Seq[(Data, BigInt)]]
  45. def parentModName: String
    Definition Classes
    HasId → InstanceId
  46. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  47. def pathName: String
    Definition Classes
    HasId → InstanceId
  48. def popCount(n: Long): Int
    Definition Classes
    BasicTester
  49. val port_to_decoupled: HashMap[Data, DecoupledIO[Data]]
  50. val port_to_valid: HashMap[Data, ValidIO[Data]]
  51. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  52. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  53. def processInputEvents(): Unit

    iterate over recorded events, checking constraints on ports referenced, etc.

    iterate over recorded events, checking constraints on ports referenced, etc. use poke and expect to record

  54. def processOutputEvents(): Unit
  55. final val reset: Reset
    Definition Classes
    Module
  56. val rnd: Random.type
    Definition Classes
    HWIOTester
  57. def stop()(implicit sourceInfo: SourceInfo): Unit
    Definition Classes
    BasicTester
  58. def suggestName(seed: => String): OrderedDecoupledHWIOTester.this.type
    Definition Classes
    HasId
  59. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  60. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  61. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  62. def toString(): String
    Definition Classes
    AnyRef → Any
  63. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  64. val valid_control_port_to_output_values: HashMap[ValidIO[Data], ArrayBuffer[TestingEvent]]
  65. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  66. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException]) @native()
  67. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable]) @Deprecated
    Deprecated
  2. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use DataMirror.fullModulePorts instead. this API will be removed in Chisel 3.6

  3. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  6. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

Inherited from HWIOTester

Inherited from BasicTester

Inherited from Module

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from internal.InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped