p

chisel3

iotesters

package iotesters

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Visibility
  1. Public
  2. Protected

Package Members

  1. package experimental

Type Members

  1. abstract class AdvTester[+T <: Module] extends PeekPokeTester[T]
  2. trait AdvTests extends PeekPokeTests
  3. class ChiselFlatSpec extends AnyFlatSpec with ChiselRunners with Matchers

    Spec base class for BDD-style testers.

  4. class ChiselPropSpec extends AnyPropSpec with ChiselRunners with ScalaCheckPropertyChecks

    Spec base class for property-based testers.

  5. trait ChiselRunners extends Assertions

    Common utility functions for Chisel unit tests.

  6. class CommandEditor extends AnyRef

    This function applies a last chance method of making final alteration of the ivl/vcs command line.

    This function applies a last chance method of making final alteration of the ivl/vcs command line. Alterations are made from a text file containing ed style regex substitutions s/regex-pattern/substitution/ or more generally s<<separator>>regex-pattern<<separator>>substitution<<separator>> if the file begins with the line verbose, the substitution parsing and operation will be logged to stdout

  7. trait EditableBuildCSimulatorCommand extends AnyRef

    An EditableBuildCSimulatorCommand provides methods for assembling a system command string from provided flags and editing specifications.

    An EditableBuildCSimulatorCommand provides methods for assembling a system command string from provided flags and editing specifications. This is a trait to facilitate expansion (for more C-based simulators) and testing.

  8. abstract class Exerciser extends BasicTester

    experimental version of a Tester that allows arbitrary testing circuitry to be run in some order

  9. abstract class HWIOTester extends BasicTester

    provide common facilities for step based testing and decoupled interface testing

  10. trait HasTesterOptions extends AnyRef
  11. class IOAccessor extends AnyRef

    named access and type information about the IO bundle of a module used for building testing harnesses

  12. abstract class OrderedDecoupledHWIOTester extends HWIOTester

    Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported.

    Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported. Testers that subclass this will be strictly ordered. Input will flow into their devices asynchronously but in order they were generated be compared in the order they are generated

    Example:

    1. class XTimesXTester extends [[OrderedDecoupledHWIOTester]] {
  val device_under_test = new XTimesY
  test_block {
    for {
      i <- 0 to 10
      j <- 0 to 10
    } {
      input_event(device_under_test.io.in.x -> i, device_under_test.in.y -> j)
      output_event(device_under_test.io.out.z -> i*j)
    }
  }
}

      an input event is a series of values that will be gated into the decoupled input interface at the same time an output event is a series of values that will be tested at the same time independent small state machines are set up for input and output interface all inputs regardless of interfaces are submitted to the device under test in the order in which they were created likewise, all outputs regardless of which interface are tested in the same order that they were created

  13. abstract class PeekPokeTester[+T <: Module] extends AnyRef
  14. trait PeekPokeTests extends AnyRef
  15. trait Pokeable[-T] extends AnyRef
    Annotations
    @implicitNotFound()
  16. trait Processable extends AnyRef
  17. class ReplOptionsManager extends InterpreterOptionsManager with HasChiselExecutionOptions with HasReplConfig
  18. abstract class SteppedHWIOTester extends HWIOTester

    Use a UnitTester to construct a test harness for a chisel module this module will be canonically referred to as the device_under_test, often simply as c in a unit test, and also dut The UnitTester is used to put series of values (as chisel3.Vec's) into the ports of the dut io which are INPUT At specified times it check the dut io OUTPUT ports to see that they match a specific value The vec's are assembled through the following API poke, expect and step, pokes

    Use a UnitTester to construct a test harness for a chisel module this module will be canonically referred to as the device_under_test, often simply as c in a unit test, and also dut The UnitTester is used to put series of values (as chisel3.Vec's) into the ports of the dut io which are INPUT At specified times it check the dut io OUTPUT ports to see that they match a specific value The vec's are assembled through the following API poke, expect and step, pokes

    Example:

    1. class Adder(width:Int) extends Module {
  val io = new Bundle {
    val in0 : UInt(INPUT, width=width)
    val in1 : UInt(INPUT, width=width)
    val out : UInt(OUTPUT, width=width)
  }
}
class AdderTester extends UnitTester {
  val device_under_test = Module( new Adder(32) )

  testBlock {
    poke(c.io.in0, 5)
    poke(c.io.in1, 7)
    expect(c.io.out, 12)
  }
}
  19. case class TesterOptions(isGenVerilog: Boolean = false, isGenHarness: Boolean = false, isCompiling: Boolean = false, isRunTest: Boolean = false, isVerbose: Boolean = false, displayBase: Int = 10, testerSeed: Long = System.currentTimeMillis, testCmd: Seq[String] = Seq.empty, moreVcsFlags: Seq[String] = Seq.empty, moreVcsCFlags: Seq[String] = Seq.empty, vcsCommandEdits: String = "", backendName: String = "treadle", logFileName: String = "", waveform: Option[File] = None, moreIvlFlags: Seq[String] = Seq.empty, moreIvlCFlags: Seq[String] = Seq.empty, ivlCommandEdits: String = "", moreVlogFlags: Seq[String] = Seq.empty, moreVsimCFlags: Seq[String] = Seq.empty, moreVsimFlags: Seq[String] = Seq.empty, moreVsimDoCmds: Seq[String] = Seq.empty, vsimCommandEdits: String = "", generateVcdOutput: String = "", generateFsdbOutput: String = "") extends ComposableOptions with Product with Serializable
  20. class TesterOptionsManager extends ExecutionOptionsManager with HasTesterOptions with HasInterpreterSuite with HasChiselExecutionOptions with HasFirrtlOptions with HasTreadleSuite

Deprecated Type Members

  1. trait HasTreadleOptions extends AnyRef
    Annotations
    @deprecated
    Deprecated

    (Since version 20210301) Use Driver#execute[T <: Module](args: Array[String], dut: () => T)

  2. trait HasTreadleSuite extends ExecutionOptionsManager with HasFirrtlOptions with HasTreadleOptions
    Annotations
    @deprecated
    Deprecated

    (Since version 20210301) Use Driver#execute[T <: Module](args: Array[String], dut: () => T)

  3. case class TreadleOptions(writeVCD: Boolean = false, enableCoverage: Boolean = false, vcdShowUnderscored: Boolean = false, setVerbose: Boolean = false, setOrderedExec: Boolean = false, allowCycles: Boolean = false, randomSeed: Long = System.currentTimeMillis(), blackBoxFactories: Seq[ScalaBlackBoxFactory] = Seq.empty, maxExecutionDepth: Long = Int.MaxValue, showFirrtlAtLoad: Boolean = false, lowCompileAtLoad: Boolean = true, validIfIsRandom: Boolean = false, rollbackBuffers: Int = 0, clockInfo: Seq[ClockInfo] = Seq.empty, resetName: String = "reset", callResetAtStartUp: Boolean = false, symbolsToWatch: Seq[String] = Seq.empty, memoryToVcd: Seq[String] = Seq.empty, saveFirrtlAtLoad: Boolean = false) extends ComposableOptions with Product with Serializable
    Annotations
    @deprecated
    Deprecated

    (Since version 20210301) Use Driver#execute[T <: Module](args: Array[String], dut: () => T)

  4. class TreadleOptionsManager extends ExecutionOptionsManager with HasTreadleSuite
    Annotations
    @deprecated
    Deprecated

    (Since version 20210301) Use Driver#execute[T <: Module](args: Array[String], dut: () => T)

Value Members

  1. object CommandEditor
  2. object Driver
  3. object DriverCompatibility

    This provides components of a compatibility wrapper around Chisel's removed chisel3.Driver.

    This provides components of a compatibility wrapper around Chisel's removed chisel3.Driver.

    Primarily, this object includes Phases that generate firrtl.annotations.Annotations derived from the deprecated firrtl.stage.phases.DriverCompatibility.TopNameAnnotation.

  4. object OrderedDecoupledHWIOTester
  5. object PeekPokeTester
  6. object Pokeable
  7. object TesterOptions extends Serializable
  8. object VerilatorCppHarnessGenerator

    Generates the Module specific verilator harness cpp file for verilator compilation

  9. object chiselMain
  10. object chiselMainTest
  11. object copyIvlFiles

    Copies the necessary header files used for iverilog compilation to the specified destination folder

  12. object copyVerilatorHeaderFiles

    Copies the necessary header files used for verilator compilation to the specified destination folder

  13. object copyVpiFiles

    Copies the necessary header files used for verilator compilation to the specified destination folder

  14. object copyVsimFiles

    Copies the necessary header files used for vlog compilation to the specified destination folder

  15. object genIVLVerilogHarness

    Generates the Module specific verilator harness cpp file for verilator compilation

  16. object genVCSVerilogHarness

    Generates the Module specific verilator harness cpp file for verilator compilation

  17. object genVSIMVerilogHarness

    Generates the Module specific vsim harness verilog file for VSIM backend

Ungrouped