CompatibilityModule

Instance Constructors

new CompatibilityModule(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions)
new CompatibilityModule(_reset: Bool)(implicit moduleCompileOptions: CompileOptions)
new CompatibilityModule(_clock: Clock)(implicit moduleCompileOptions: CompileOptions)
new CompatibilityModule(override_clock: Option[Clock] = None, override_reset: Option[Bool] = None)(implicit moduleCompileOptions: CompileOptions)
new CompatibilityModule()(implicit moduleCompileOptions: CompileOptions)

Abstract Value Members

abstract def io: chisel3.Record

Definition Classes
LegacyModule

Concrete Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def IO[T <: chisel3.Data](iodef: T): T

Attributes
protected
Definition Classes
BaseModule
def _bindIoInPlace(iodef: chisel3.Data): Unit

Attributes
protected
Definition Classes
BaseModule
var _closed: Boolean

Attributes
protected
Definition Classes
BaseModule
def _compatAutoWrapPorts(): Unit

Definition Classes
CompatibilityModule → BaseModule
def _compatIoPortBound(): Boolean

Attributes
protected
Definition Classes
LegacyModule
final def asInstanceOf[T0]: T0

Definition Classes
Any
def circuitName: String

Attributes
protected
Definition Classes
HasId
final val clock: chisel3.Clock

Definition Classes
MultiIOModule
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
val compileOptions: CompileOptions

Definition Classes
RawModule
def desiredName: String

Definition Classes
BaseModule
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(that: Any): Boolean

Definition Classes
HasId → AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getCommands: Seq[Command]

Attributes
protected
Definition Classes
RawModule
def getIds: Seq[HasId]

Attributes
protected
Definition Classes
BaseModule
def getModulePorts: Seq[chisel3.Data]

Attributes
protected[chisel3]
Definition Classes
BaseModule
lazy val getPorts: Seq[Port]

Definition Classes
RawModule
def hashCode(): Int

Definition Classes
HasId → AnyRef → Any
def instanceName: String

Definition Classes
BaseModule → HasId → InstanceId
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
final lazy val name: String

Definition Classes
BaseModule
def nameIds(rootClass: Class[_]): HashMap[HasId, String]

Attributes
protected
Definition Classes
BaseModule
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
var override_clock: Option[chisel3.Clock]

Attributes
protected
Definition Classes
LegacyModule
var override_reset: Option[chisel3.Bool]

Attributes
protected
Definition Classes
LegacyModule
def parentModName: String

Definition Classes
HasId → InstanceId
def parentPathName: String

Definition Classes
HasId → InstanceId
def pathName: String

Definition Classes
HasId → InstanceId
def portsContains(elem: chisel3.Data): Boolean

Attributes
protected
Definition Classes
BaseModule
def portsSize: Int

Attributes
protected
Definition Classes
BaseModule
final val reset: chisel3.Reset

Definition Classes
MultiIOModule
def suggestName(name: ⇒ String): CompatibilityModule.this.type

Definition Classes
HasId
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
final def toAbsoluteTarget: IsModule

Definition Classes
BaseModule → InstanceId
final def toNamed: ModuleName

Definition Classes
BaseModule → InstanceId
def toString(): String

Definition Classes
AnyRef → Any
final def toTarget: ModuleTarget

Definition Classes
BaseModule → InstanceId
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )

Related Doc: package Chisel

abstract class CompatibilityModule extends LegacyModule

Instance Constructors

new CompatibilityModule(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions)

new CompatibilityModule(_reset: Bool)(implicit moduleCompileOptions: CompileOptions)

new CompatibilityModule(_clock: Clock)(implicit moduleCompileOptions: CompileOptions)

new CompatibilityModule(override_clock: Option[Clock] = None, override_reset: Option[Bool] = None)(implicit moduleCompileOptions: CompileOptions)

new CompatibilityModule()(implicit moduleCompileOptions: CompileOptions)

Abstract Value Members

abstract def io: chisel3.Record

Concrete Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def IO[T <: chisel3.Data](iodef: T): T

def _bindIoInPlace(iodef: chisel3.Data): Unit

var _closed: Boolean

def _compatAutoWrapPorts(): Unit

def _compatIoPortBound(): Boolean

final def asInstanceOf[T0]: T0

def circuitName: String

final val clock: chisel3.Clock

def clone(): AnyRef

val compileOptions: CompileOptions

def desiredName: String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

final def getClass(): Class[_]

def getCommands: Seq[Command]

def getIds: Seq[HasId]

def getModulePorts: Seq[chisel3.Data]

lazy val getPorts: Seq[Port]

def hashCode(): Int

def instanceName: String

final def isInstanceOf[T0]: Boolean

final lazy val name: String

def nameIds(rootClass: Class[_]): HashMap[HasId, String]

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

var override_clock: Option[chisel3.Clock]

var override_reset: Option[chisel3.Bool]

def parentModName: String

def parentPathName: String

def pathName: String

def portsContains(elem: chisel3.Data): Boolean

def portsSize: Int

final val reset: chisel3.Reset

def suggestName(name: ⇒ String): CompatibilityModule.this.type

final def synchronized[T0](arg0: ⇒ T0): T0

final def toAbsoluteTarget: IsModule

final def toNamed: ModuleName

def toString(): String

final def toTarget: ModuleTarget

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

Inherited from LegacyModule

Inherited from MultiIOModule

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped