object Pipe
A factory to generate a hardware pipe. This can be used to delay Valid data by a design-time configurable number of cycles.
Here, we construct three different pipes using the different provided apply
methods and hook them up together. The
types are explicitly specified to show that these all communicate using Valid interfaces:
val in: Valid[UInt] = Wire(Valid(UInt(2.W))) /* A zero latency (combinational) pipe is connected to 'in' */ val foo: Valid[UInt] = Pipe(in.valid, in.bits, 0) /* A one-cycle pipe is connected to the output of 'foo' */ val bar: Valid[UInt] = Pipe(foo.valid, foo.bits) /* A two-cycle pipe is connected to the output of 'bar' */ val baz: Valid[UInt] = Pipe(bar, 2)
- Source
- Valid.scala
- See also
Pipe class for an alternative API
Valid interface
Queue and the Queue factory for actual queues
The ShiftRegister factory to generate a pipe without a Valid interface
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def
apply[T <: Data](enq: Valid[T], latency: Int = 1)(implicit compileOptions: CompileOptions): Valid[T]
Generate a pipe for a Valid interface
-
def
apply[T <: Data](enqValid: Bool, enqBits: T)(implicit compileOptions: CompileOptions): Valid[T]
Generate a one-stage pipe from an explicit valid bit and some data
Generate a one-stage pipe from an explicit valid bit and some data
- enqValid
the valid bit (must be a hardware type)
- enqBits
the data (must be a hardware type)
- returns
the Valid output of the final pipeline stage
-
def
apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T]
Generate a pipe from an explicit valid bit and some data
Generate a pipe from an explicit valid bit and some data
- enqValid
the valid bit (must be a hardware type)
- enqBits
the data (must be a hardware type)
- latency
the number of pipeline stages
- returns
the Valid output of the final pipeline stage
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,FixedPoint
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.