Type Members

1.  class Arbiter[T <: Data] extends Module

   Hardware module that is used to sequence n producers into 1 consumer.

   Hardware module that is used to sequence n producers into 1 consumer. Priority is given to lower producer.

   Example:

   1. val arb = Module(new Arbiter(UInt(), 2))
      arb.io.in(0) <> producer0.io.out
      arb.io.in(1) <> producer1.io.out
      consumer.io.in <> arb.io.out

2.  class ArbiterIO[T <: Data] extends Bundle

   IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs (selects) at most one.

3.  sealed class BitPat extends SourceInfoDoc

   Bit patterns are literals with masks, used to represent values with don't care bits.

   Bit patterns are literals with masks, used to represent values with don't care bits. Equality comparisons will ignore don't care bits.

   Example:

   1. "b10101".U === BitPat("b101??") // evaluates to true.B
      "b10111".U === BitPat("b101??") // evaluates to true.B
      "b10001".U === BitPat("b101??") // evaluates to false.B

4.  class Counter extends AnyRef

   Used to generate an inline (logic directly in the containing Module, no internal Module is created) hardware counter.

   Used to generate an inline (logic directly in the containing Module, no internal Module is created) hardware counter.

   Typically instantiated with apply methods in object Counter

   Does not create a new Chisel Module

   Example:

   1. val countOn = true.B // increment counter every clock cycle
      val (counterValue, counterWrap) = Counter(countOn, 4)
      when (counterValue === 3.U) {
        ...
      }

5.  class DecoupledIO[+T <: Data] extends ReadyValidIO[T]

   A concrete subclass of ReadyValidIO signaling that the user expects a "decoupled" interface: 'valid' indicates that the producer has put valid data in 'bits', and 'ready' indicates that the consumer is ready to accept the data this cycle.

   A concrete subclass of ReadyValidIO signaling that the user expects a "decoupled" interface: 'valid' indicates that the producer has put valid data in 'bits', and 'ready' indicates that the consumer is ready to accept the data this cycle. No requirements are placed on the signaling of ready or valid.

6.  trait Enum extends AnyRef

   Defines a set of unique UInt constants

   Defines a set of unique UInt constants

   Unpack with a list to specify an enumeration. Usually used with switch to describe a finite state machine.

   Example:

   1. val state_on :: state_off :: Nil = Enum(2)
      val current_state = WireDefault(state_off)
      switch (current_state) {
        is (state_on) {
          ...
        }
        is (state_off) {
          ...
        }
      }

7.  trait HasBlackBoxInline extends BlackBox
8.  trait HasBlackBoxPath extends BlackBox
9.  trait HasBlackBoxResource extends BlackBox
10.  class IrrevocableIO[+T <: Data] extends ReadyValidIO[T]

    A concrete subclass of ReadyValidIO that promises to not change the value of 'bits' after a cycle where 'valid' is high and 'ready' is low.

    A concrete subclass of ReadyValidIO that promises to not change the value of 'bits' after a cycle where 'valid' is high and 'ready' is low. Additionally, once 'valid' is raised it will never be lowered until after 'ready' has also been raised.

11.  class LockingArbiter[T <: Data] extends LockingArbiterLike[T]
12.  abstract class LockingArbiterLike[T <: Data] extends Module
13.  class LockingRRArbiter[T <: Data] extends LockingArbiterLike[T]
14.  final class MixedVec[T <: Data] extends Record with IndexedSeq[T]

    A hardware array of elements that can hold values of different types/widths, unlike Vec which can only hold elements of the same type/width.

    A hardware array of elements that can hold values of different types/widths, unlike Vec which can only hold elements of the same type/width.

    Example:

    1. val v = Wire(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(32.W))))
       v(0) := 100.U(8.W)
       v(1) := 10000.U(16.W)
       v(2) := 101.U(32.W)

15.  class Pipe[T <: Data] extends Module

    Pipeline module generator parameterized by data type and latency.

    Pipeline module generator parameterized by data type and latency.

    This defines a module with one input, enq, and one output, deq. The input and output are Valid interfaces that wrap some Chisel type, e.g., a UInt or a Bundle. This generator will then chain together a number of pipeline stages that all advance when the input Valid enq fires. The output deq Valid will fire only when valid data has made it all the way through the pipeline.

    As an example, to construct a 4-stage pipe of 8-bit UInts and connect it to a producer and consumer, you can use the following:

    val foo = Module(new Pipe(UInt(8.W)), 4)
    pipe.io.enq := producer.io
    consumer.io := pipe.io.deq

    If you already have the Valid input or the components of a Valid interface, it may be simpler to use the Pipe factory companion object. This, which Pipe internally utilizes, will automatically connect the input for you.

    See also

    Pipe factory for an alternative API

    Valid interface

    Queue and the Queue factory for actual queues

    The ShiftRegister factory to generate a pipe without a Valid interface

16.  class Queue[T <: Data] extends Module

    A hardware module implementing a Queue

    A hardware module implementing a Queue

    Example:

    1. val q = Module(new Queue(UInt(), 16))
       q.io.enq <> producer.io.out
       consumer.io.in <> q.io.deq

17.  class QueueIO[T <: Data] extends Bundle

    An I/O Bundle for Queues

18.  class RRArbiter[T <: Data] extends LockingRRArbiter[T]

    Hardware module that is used to sequence n producers into 1 consumer.

    Hardware module that is used to sequence n producers into 1 consumer. Producers are chosen in round robin order.

    Example:

    1. val arb = Module(new RRArbiter(UInt(), 2))
       arb.io.in(0) <> producer0.io.out
       arb.io.in(1) <> producer1.io.out
       consumer.io.in <> arb.io.out

19.  abstract class ReadyValidIO[+T <: Data] extends Bundle

    An I/O Bundle containing 'valid' and 'ready' signals that handshake the transfer of data stored in the 'bits' subfield.

    An I/O Bundle containing 'valid' and 'ready' signals that handshake the transfer of data stored in the 'bits' subfield. The base protocol implied by the directionality is that the producer uses the interface as-is (outputs bits) while the consumer uses the flipped interface (inputs bits). The actual semantics of ready/valid are enforced via the use of concrete subclasses.

20.  class SwitchContext[T <: Element] extends AnyRef

    Implementation details for switch.

    Implementation details for switch. See switch and is for the user-facing API.

    Note

    DO NOT USE. This API is subject to change without warning.

21.  class Valid[+T <: Data] extends Bundle

    A Bundle that adds a valid bit to some data.

    A Bundle that adds a valid bit to some data. This indicates that the user expects a "valid" interface between a producer and a consumer. Here, the producer asserts the valid bit when data on the bits line contains valid data. This differs from DecoupledIO or IrrevocableIO as there is no ready line that the consumer can use to put back pressure on the producer.

    In most scenarios, the Valid class will not be used directly. Instead, users will create Valid interfaces using the Valid factory.

    T

    the type of the data

    See also

    Valid factory for concrete examples

22.  type ValidIO[+T <: Data] = Valid[T]

    Synonyms, moved from main package object - maintain scope.