class LoadMemoryTransform extends Transform
This transform only is activated if Verilog is being generated (determined by presence of the proper emit annotation) when activated it creates additional Verilog files that contain modules bound to the modules that contain an initializable memory
Currently the only non-Verilog based simulation that can support loading memory from a file is treadle but it does not need this transform to do that.
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inputForm: CircuitForm
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def
run(circuit: Circuit, annotations: AnnotationSeq): Circuit
run the pass
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the circuit
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all the annotations
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(Since version 1.1) Just collect the actual Annotation types the transform wants
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,FixedPoint
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.