Packages

p

Chisel

package Chisel

Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. Chisel
  2. AnyRef
  3. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Type Members

  1. implicit class AddDirMethodToData[T <: Data] extends AnyRef
  2. implicit class AddDirectionToData[T <: Data] extends AnyRef
  3. type Aggregate = chisel3.Aggregate
  4. type Arbiter[T <: Data] = chisel3.util.Arbiter[T]
  5. type ArbiterIO[T <: Data] = chisel3.util.ArbiterIO[T]
  6. type BackendCompilationUtilities = firrtl.util.BackendCompilationUtilities
  7. type BitPat = chisel3.util.BitPat
  8. type Bits = chisel3.Bits
  9. implicit class BitsCompatibility extends AnyRef
  10. implicit class BitsObjectCompatibility extends AnyRef
  11. abstract class BlackBox extends chisel3.BlackBox
  12. type Bool = chisel3.Bool
  13. trait BoolFactory extends chisel3.BoolFactory

    This contains literal constructor factory methods that are deprecated as of Chisel3.

  14. type Bundle = chisel3.Bundle
  15. type ChiselException = chisel3.internal.ChiselException
  16. type Clock = chisel3.Clock
  17. abstract class CompatibilityModule extends LegacyModule
  18. type Counter = chisel3.util.Counter
  19. type Data = chisel3.Data
  20. implicit class DataCompatibility extends AnyRef
  21. type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
  22. abstract class Direction extends AnyRef
  23. type Element = chisel3.Element
  24. type LockingArbiter[T <: Data] = chisel3.util.LockingArbiter[T]
  25. type LockingArbiterLike[T <: Data] = chisel3.util.LockingArbiterLike[T]
  26. type LockingRRArbiter[T <: Data] = chisel3.util.LockingRRArbiter[T]
  27. type Mem[T <: Data] = chisel3.Mem[T]
  28. type MemBase[T <: Data] = chisel3.MemBase[T]
  29. implicit class MemCompatibility extends AnyRef
  30. type Module = CompatibilityModule
  31. type Num[T <: Data] = chisel3.Num[T]
  32. type Pipe[T <: Data] = chisel3.util.Pipe[T]
  33. type Queue[T <: Data] = QueueCompatibility[T]
  34. sealed class QueueCompatibility[T <: Data] extends chisel3.util.Queue[T]
  35. type QueueIO[T <: Data] = chisel3.util.QueueIO[T]
  36. type RRArbiter[T <: Data] = chisel3.util.RRArbiter[T]
  37. type Record = chisel3.Record
  38. type Reset = chisel3.Reset
  39. type SInt = chisel3.SInt
  40. trait SIntFactory extends chisel3.SIntFactory

    This contains literal constructor factory methods that are deprecated as of Chisel3.

  41. type SeqMem[T <: Data] = SyncReadMem[T]
  42. implicit class SeqMemCompatibility extends AnyRef
  43. type SwitchContext[T <: Bits] = chisel3.util.SwitchContext[T]
  44. type UInt = chisel3.UInt
  45. trait UIntFactory extends chisel3.UIntFactory

    This contains literal constructor factory methods that are deprecated as of Chisel3.

  46. type ValidIO[+T <: Data] = Valid[T]
  47. type Vec[T <: Data] = chisel3.Vec[T]
  48. type VecLike[T <: Data] = chisel3.VecLike[T]
  49. implicit class VecLikeCompatibility[T <: Data] extends AnyRef
  50. type WhenContext = chisel3.WhenContext
  51. implicit class cloneTypeable[T <: Data] extends AnyRef
  52. implicit class fromBigIntToLiteral extends chisel3.fromBigIntToLiteral
  53. implicit class fromBitsable[T <: Data] extends AnyRef
  54. implicit class fromBooleanToLiteral extends chisel3.fromBooleanToLiteral
  55. implicit class fromIntToWidth extends chisel3.fromIntToWidth
  56. implicit class fromStringToLiteral extends chisel3.fromStringToLiteral
  57. implicit class fromtIntToLiteral extends fromIntToLiteral
  58. implicit class fromtLongToLiteral extends fromLongToLiteral

Value Members

  1. val BitPat: chisel3.util.BitPat.type
  2. val Cat: chisel3.util.Cat.type
  3. val Counter: chisel3.util.Counter.type
  4. val Decoupled: chisel3.util.Decoupled.type
  5. val DecoupledIO: chisel3.util.Decoupled.type
  6. val Fill: chisel3.util.Fill.type
  7. val FillInterleaved: chisel3.util.FillInterleaved.type
  8. val ImplicitConversions: chisel3.util.ImplicitConversions.type
  9. val Input: chisel3.Input.type
  10. val ListLookup: chisel3.util.ListLookup.type
  11. val Log2: chisel3.util.Log2.type
  12. val Lookup: chisel3.util.Lookup.type
  13. val Mem: chisel3.Mem.type
  14. val Module: chisel3.Module.type
  15. val Mux: chisel3.Mux.type
  16. val Mux1H: chisel3.util.Mux1H.type
  17. val MuxCase: chisel3.util.MuxCase.type
  18. val MuxLookup: chisel3.util.MuxLookup.type
  19. val OHToUInt: chisel3.util.OHToUInt.type
  20. val Output: chisel3.Output.type
  21. val Pipe: chisel3.util.Pipe.type
  22. val PopCount: chisel3.util.PopCount.type
  23. val PriorityEncoder: chisel3.util.PriorityEncoder.type
  24. val PriorityEncoderOH: chisel3.util.PriorityEncoderOH.type
  25. val PriorityMux: chisel3.util.PriorityMux.type
  26. val Queue: chisel3.util.Queue.type
  27. val RegEnable: chisel3.util.RegEnable.type
  28. val RegInit: chisel3.RegInit.type
  29. val RegNext: chisel3.RegNext.type
  30. val Reverse: chisel3.util.Reverse.type
  31. val SeqMem: SyncReadMem.type
  32. val ShiftRegister: chisel3.util.ShiftRegister.type
  33. val UIntToOH: chisel3.util.UIntToOH.type
  34. val Valid: chisel3.util.Valid.type
  35. val assert: chisel3.assert.type
  36. implicit val defaultCompileOptions: CompileOptionsClass
  37. val is: chisel3.util.is.type
  38. val isPow2: chisel3.util.isPow2.type
  39. val log2Ceil: chisel3.util.log2Ceil.type
  40. val log2Floor: chisel3.util.log2Floor.type
  41. val printf: chisel3.printf.type
  42. implicit def resetToBool(reset: Reset): Bool
  43. val stop: chisel3.stop.type
  44. val switch: chisel3.util.switch.type
  45. val unless: chisel3.util.unless.type
  46. val when: chisel3.when.type
  47. object Bits extends UIntFactory
  48. object Bool extends BoolFactory
  49. object Clock
  50. object Enum extends Enum
  51. object Flipped
  52. object INPUT extends Direction with Product with Serializable
  53. object LFSR16

    LFSR16 generates a 16-bit linear feedback shift register, returning the register contents.

    LFSR16 generates a 16-bit linear feedback shift register, returning the register contents. This is useful for generating a pseudo-random sequence.

    The example below, taken from the unit tests, creates two 4-sided dice using LFSR16 primitives:

    Example: 

    1. val bins = Reg(Vec(8, UInt(32.W)))

// Create two 4 sided dice and roll them each cycle.
// Use tap points on each LFSR so values are more independent
val die0 = Cat(Seq.tabulate(2) { i => LFSR16()(i) })
val die1 = Cat(Seq.tabulate(2) { i => LFSR16()(i + 2) })

val rollValue = die0 +& die1  // Note +& is critical because sum will need an extra bit.

bins(rollValue) := bins(rollValue) + 1.U
  54. object NODIR extends Direction with Product with Serializable
  55. object OUTPUT extends Direction with Product with Serializable
  56. object Reg
  57. object SInt extends SIntFactory
  58. object UInt extends UIntFactory
  59. object Vec extends VecFactory
  60. object Wire extends WireFactory
  61. object chiselMain
  62. object experimental

    Package for experimental features, which may have their API changed, be removed, etc.

    Package for experimental features, which may have their API changed, be removed, etc.

    Because its contents won't necessarily have the same level of stability and support as non-experimental, you must explicitly import this package to use its contents.

  63. object log2Down

    Compute the log2 rounded down with min value of 1

  64. object log2Up

    Compute the log2 rounded up with min value of 1

  65. object testers
  66. object throwException
    Annotations
    @throws( classOf[Exception] )

Deprecated Value Members

  1. val Driver: chisel3.Driver.type
    Annotations
    @deprecated
    Deprecated

    (Since version 3.4) Please switch to chisel3.stage.ChiselStage

  2. object debug
    Annotations
    @deprecated
    Deprecated

    (Since version chisel3) debug doesn't do anything in Chisel3 as no pruning happens in the frontend

Inherited from AnyRef

Inherited from Any

Ungrouped