Packages

class Pipe[T <: Data] extends Module

Pipeline module generator parameterized by data type and latency.

This defines a module with one input, enq, and one output, deq. The input and output are Valid interfaces that wrap some Chisel type, e.g., a UInt or a Bundle. This generator will then chain together a number of pipeline stages that all advance when the input Valid enq fires. The output deq Valid will fire only when valid data has made it all the way through the pipeline.

As an example, to construct a 4-stage pipe of 8-bit UInts and connect it to a producer and consumer, you can use the following:

val foo = Module(new Pipe(UInt(8.W)), 4)
pipe.io.enq := producer.io
consumer.io := pipe.io.deq

If you already have the Valid input or the components of a Valid interface, it may be simpler to use the Pipe factory companion object. This, which Pipe internally utilizes, will automatically connect the input for you.

Source
Valid.scala
See also

Pipe factory for an alternative API

Valid interface

Queue and the Queue factory for actual queues

The ShiftRegister factory to generate a pipe without a Valid interface

Linear Supertypes
Module, RawModule, BaseModule, IsInstantiable, HasId, internal.InstanceId, AnyRef, Any
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Inherited
  1. Pipe
  2. Module
  3. RawModule
  4. BaseModule
  5. IsInstantiable
  6. HasId
  7. InstanceId
  8. AnyRef
  9. Any
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Visibility
  1. Public
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Instance Constructors

  1. new Pipe(gen: T, latency: Int = 1)(implicit compileOptions: CompileOptions)

    gen

    a Chisel type

    latency

    the number of pipeline stages

Type Members

  1. class PipeIO extends Bundle

    Interface for Pipes composed of a Valid input and Valid output

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  9. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  10. final val clock: Clock
    Definition Classes
    Module
  11. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  12. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  13. def desiredName: String
    Definition Classes
    BaseModule
  14. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  15. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  16. val gen: T
  17. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  18. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  19. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  20. def hasSeed: Boolean
    Definition Classes
    HasId
  21. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  22. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  23. val io: PipeIO
  24. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  25. val latency: Int
  26. final lazy val name: String
    Definition Classes
    BaseModule
  27. def nameIds(rootClass: Class[_]): HashMap[HasId, String]
    Attributes
    protected
    Definition Classes
    BaseModule
  28. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  29. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  30. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  31. def parentModName: String
    Definition Classes
    HasId → InstanceId
  32. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  33. def pathName: String
    Definition Classes
    HasId → InstanceId
  34. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  35. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  36. final val reset: Reset
    Definition Classes
    Module
  37. def suggestName(seed: ⇒ String): Pipe.this.type
    Definition Classes
    HasId
  38. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  39. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  40. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  41. def toString(): String
    Definition Classes
    AnyRef → Any
  42. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  43. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  44. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  45. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated
  2. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use DataMirror.modulePorts instead. this API will be removed in Chisel 3.6

  3. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  6. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

Inherited from Module

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from internal.InstanceId

Inherited from AnyRef

Inherited from Any

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