trait HasExtModuleInline extends ExtModule
Ordering
- Alphabetic
- By Inheritance
Inherited
- HasExtModuleInline
- ExtModule
- BaseBlackBox
- BaseModule
- IsInstantiable
- HasId
- InstanceId
- AnyRef
- Any
- Hide All
- Show All
Visibility
- Public
- Protected
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: T): T
- Attributes
- protected
- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _compatAutoWrapPorts(): Unit
- Definition Classes
- BaseModule
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- def desiredName: String
- Definition Classes
- BaseModule
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- final lazy val name: String
- Definition Classes
- BaseModule
- def nameIds(rootClass: Class[_]): HashMap[HasId, String]
- Attributes
- protected
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- val params: Map[String, Param]
- Definition Classes
- ExtModule
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- def setInline(blackBoxName: String, blackBoxInline: String): Unit
Creates a black box verilog file, from the contents of a local string
Creates a black box verilog file, from the contents of a local string
- blackBoxName
The black box module name, to create filename
- blackBoxInline
The black box contents
- def suggestName(seed: => String): HasExtModuleInline.this
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,FixedPoint,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.