Check if two Chisel types are the same type. Internally, this is dispatched to each Chisel type's typeEquivalent function for each type to determine if the types are intended to be equal.

For most types, different parameters should ensure that the types are different. For example, UInt(8.W) and UInt(16.W) are different. Likewise, Records check that both Records have the same elements with the same types.

Returns a recursive representation of a module's ports with underscore-qualified names

class MyModule extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(8.W))
    val out = Output(Vec(2, UInt(8.W)))
  })
  val extra = IO(Input(UInt(8.W)))
  val delay = RegNext(io.in)
  io.out(0) := delay
  io.out(1) := delay + extra
}
val mod = Module(new MyModule)
DataMirror.fullModulePorts(mod)
// returns: Seq(
//   "clock" -> mod.clock,
//   "reset" -> mod.reset,
//   "io" -> mod.io,
//   "io_out" -> mod.io.out,
//   "io_out_0" -> mod.io.out(0),
//   "io_out_1" -> mod.io.out(1),
//   "io_in" -> mod.io.in,
//   "extra" -> mod.extra
// )

Check if a given Data is an IO port

Check if a given Data is a Reg

Check if a given Data is a Wire

Returns the ports of a module

class MyModule extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(8.W))
    val out = Output(Vec(2, UInt(8.W)))
  })
  val extra = IO(Input(UInt(8.W)))
  val delay = RegNext(io.in)
  io.out(0) := delay
  io.out(1) := delay + extra
}
val mod = Module(new MyModule)
DataMirror.modulePorts(mod)
// returns: Seq(
//   "clock" -> mod.clock,
//   "reset" -> mod.reset,
//   "io" -> mod.io,
//   "extra" -> mod.extra
// )