AsyncFifo

Instance Constructors

new AsyncFifo(gen: T, entries: Int, enq_clk: Clock, deq_clk: Clock)

gen
the type of data in the fifo
entries
the max number of entries in the fifo. The actual size will be rounded up to the next power of 2 - (size = 1<<log2Up(entries))
enq_clk
clock for the input (writing, queuing) side
deq_clk
clock for the output (reading, dequeuing side) side

Type Members

type neededWireWraps = HashMap[StackTraceElement, ArrayBuffer[Data]]

verifyWireWrap (Chisel3) - verify assignment semantics (type-only nodes must be wire-wrapped)
verifyWireWrap (Chisel3) - verify assignment semantics (type-only nodes must be wire-wrapped)
returns
- HashMap of source lines (and associated nodes) requiring Wire() wrapping.

Definition Classes
Module

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
def <>(src: Module): Unit

Connect io with matching names for two modules
Connect io with matching names for two modules

Definition Classes
Module
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
var _clock: Option[Clock]

Definition Classes
Module
def addClock(clock: Clock): Unit

Add a clock to the module
Add a clock to the module
clock
the clock to add

Definition Classes
Module
def addDefaultReset: Unit

Add a default reset to the module
Add a default reset to the module

Definition Classes
Module
def addModule[T <: Module](c: ⇒ T)(implicit p: Parameters = params): T

Add a submodule to this module
Add a submodule to this module

Definition Classes
Module
def addModule[T <: Module](c: ⇒ T, f: PartialFunction[Any, Any]): T

Add a submodule to this module
Add a submodule to this module

Definition Classes
Module
def addPin[T <: Data](pin: T, name: String = ""): T

Add a pin with a name to the module
Add a pin with a name to the module
pin
the I/O to add
name
A name for the pin

Definition Classes
Module
def addResetPin(r: Bool): Bool

returns
the pin connected to the reset signal or creates a new one if no such pin exists

Definition Classes
Module
def apply(name: String): Data

Definition Classes
Module
final def asInstanceOf[T0]: T0

Definition Classes
Any
val asize: Int
def assert(cond: Bool, message: String): Unit

Add an assertion in the code generated by a backend.
Add an assertion in the code generated by a backend.

Definition Classes
Module
def bfs(visit: (Node) ⇒ Unit): Unit

A breadth first search of the graph of nodes
A breadth first search of the graph of nodes

Definition Classes
Module
val children: ArrayBuffer[Module]

Definition Classes
Module
def clock: Clock

returns
the implied clock for this module

Definition Classes
Module
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
def debug(x: Node): Unit

Insures a backend does not remove a signal because it is unreachable from the outputs.
Insures a backend does not remove a signal because it is unreachable from the outputs.

Definition Classes
Module
def dfs(visit: (Node) ⇒ Unit): Unit

A depth first search of the graph of nodes
A depth first search of the graph of nodes

Definition Classes
Module
def emitDec(b: Backend): String

Definition Classes
Module
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(that: Any): Boolean

Definition Classes
Module → AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
def findBinding(m: Node): Option[Binding]

A method to trace the graph of nodes backwards looking at inputs
A method to trace the graph of nodes backwards looking at inputs
m
Node to find bindings for
returns
nodes which have node m binded as their input

Definition Classes
Module
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getPathName(separator: String = "_"): String

separator
The separator to use for the path name
returns
the absolute path to a component instance from toplevel

Definition Classes
Module
def getPathName: String

returns
the absolute path to a component instance from toplevel

Definition Classes
Module
val hashCode: Int

Definition Classes
Module → AnyRef → Any
val io: QueueIO[T]

the I/O for this module
the I/O for this module

Definition Classes
AsyncFifo → Module
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
val mem: Mem[T]
var moduleName: String

Name of the module this component generates (defaults to class name).
Name of the module this component generates (defaults to class name).

Definition Classes
Module
var name: String

Name of the instance.
Name of the instance.

Definition Classes
Module
var named: Boolean

Definition Classes
Module
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def nextIndex: Int

Definition Classes
Module
var nindex: Option[Int]

Definition Classes
Module
val not_empty: Bool
val not_empty_next: Bool
val not_full: Bool
val not_full_next: Bool
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
lazy val params: Parameters

Definition Classes
Module
var parent: Module

Definition Classes
Module
def printf(message: String, args: Node*): Unit

Adds a printf to the module called each clock cycle
Adds a printf to the module called each clock cycle
message
A c style sting to print out eg) %d, %x
args
Nodes whos data values should be printed

Definition Classes
Module
def reset: Bool

returns
the implied reset for this module

Definition Classes
Module
def reset_=(r: Bool): Unit

Definition Classes
Module
val rptr_bin: UInt
val rptr_bin_next: UInt
val rptr_gray: UInt
val rptr_gray_next: UInt
val s1_rptr_gray: UInt
val s1_rst_deq: Bool
val s1_rst_enq: Bool
val s1_wptr_gray: UInt
val s2_rptr_gray: UInt
val s2_rst_deq: Bool
val s2_rst_enq: Bool
val s2_wptr_gray: UInt
def setModuleName(n: String): Unit

Set the declaration name of the module to be string 'n'
Set the declaration name of the module to be string 'n'

Definition Classes
Module
def setName(n: String): Unit

Set the name of this module to the string 'n'
Set the name of this module to the string 'n'

Definition Classes
Module
def stripComponent(s: String): String

Definition Classes
Module
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
Module → AnyRef → Any
var verilog_parameters: String

Definition Classes
Module
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
def wires: Array[(String, Bits)]

Get the I/O names and connections
Get the I/O names and connections

Definition Classes
Module
val wptr_bin: UInt
val wptr_bin_next: UInt
val wptr_gray: UInt
val wptr_gray_next: UInt

Related Doc: package Chisel

class AsyncFifo[T <: Data] extends Module

Instance Constructors

new AsyncFifo(gen: T, entries: Int, enq_clk: Clock, deq_clk: Clock)

Type Members

type neededWireWraps = HashMap[StackTraceElement, ArrayBuffer[Data]]

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

def <>(src: Module): Unit

final def ==(arg0: Any): Boolean

var _clock: Option[Clock]

def addClock(clock: Clock): Unit

def addDefaultReset: Unit

def addModule[T <: Module](c: ⇒ T)(implicit p: Parameters = params): T

def addModule[T <: Module](c: ⇒ T, f: PartialFunction[Any, Any]): T

def addPin[T <: Data](pin: T, name: String = ""): T

def addResetPin(r: Bool): Bool

def apply(name: String): Data

final def asInstanceOf[T0]: T0

val asize: Int

def assert(cond: Bool, message: String): Unit

def bfs(visit: (Node) ⇒ Unit): Unit

val children: ArrayBuffer[Module]

def clock: Clock

def clone(): AnyRef

def debug(x: Node): Unit

def dfs(visit: (Node) ⇒ Unit): Unit

def emitDec(b: Backend): String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

def findBinding(m: Node): Option[Binding]

final def getClass(): Class[_]

def getPathName(separator: String = "_"): String

def getPathName: String

val hashCode: Int

val io: QueueIO[T]

final def isInstanceOf[T0]: Boolean

val mem: Mem[T]

var moduleName: String

var name: String

var named: Boolean

final def ne(arg0: AnyRef): Boolean

def nextIndex: Int

var nindex: Option[Int]

val not_empty: Bool

val not_empty_next: Bool

val not_full: Bool

val not_full_next: Bool

final def notify(): Unit

final def notifyAll(): Unit

lazy val params: Parameters

var parent: Module

def printf(message: String, args: Node*): Unit

def reset: Bool

def reset_=(r: Bool): Unit

val rptr_bin: UInt

val rptr_bin_next: UInt

val rptr_gray: UInt

val rptr_gray_next: UInt

val s1_rptr_gray: UInt

val s1_rst_deq: Bool

val s1_rst_enq: Bool

val s1_wptr_gray: UInt

val s2_rptr_gray: UInt

val s2_rst_deq: Bool

val s2_rst_enq: Bool

val s2_wptr_gray: UInt

def setModuleName(n: String): Unit

def setName(n: String): Unit

def stripComponent(s: String): String

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

var verilog_parameters: String

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

def wires: Array[(String, Bits)]