Module

Instance Constructors

new Module(_clock: Option[Clock] = None, _reset: Option[Bool] = None)

Type Members

type neededWireWraps = HashMap[StackTraceElement, ArrayBuffer[Data]]

verifyWireWrap (Chisel3) - verify assignment semantics (type-only nodes must be wire-wrapped)
verifyWireWrap (Chisel3) - verify assignment semantics (type-only nodes must be wire-wrapped)
returns
- HashMap of source lines (and associated nodes) requiring Wire() wrapping.

Abstract Value Members

abstract def io: Data

the I/O for this module

Concrete Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
def <>(src: Module): Unit

Connect io with matching names for two modules
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
var _clock: Option[Clock]
def addClock(clock: Clock): Unit

Add a clock to the module
Add a clock to the module
clock
the clock to add
def addDefaultReset: Unit

Add a default reset to the module
def addModule[T <: Module](c: ⇒ T)(implicit p: Parameters = params): T

Add a submodule to this module
def addModule[T <: Module](c: ⇒ T, f: PartialFunction[Any, Any]): T

Add a submodule to this module
def addPin[T <: Data](pin: T, name: String = ""): T

Add a pin with a name to the module
Add a pin with a name to the module
pin
the I/O to add
name
A name for the pin
def addResetPin(r: Bool): Bool

returns
the pin connected to the reset signal or creates a new one if no such pin exists
def apply(name: String): Data
final def asInstanceOf[T0]: T0

Definition Classes
Any
def assert(cond: Bool, message: String): Unit

Add an assertion in the code generated by a backend.
def bfs(visit: (Node) ⇒ Unit): Unit

A breadth first search of the graph of nodes
val children: ArrayBuffer[Module]
def clock: Clock

returns
the implied clock for this module
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
def debug(x: Node): Unit

Insures a backend does not remove a signal because it is unreachable from the outputs.
def dfs(visit: (Node) ⇒ Unit): Unit

A depth first search of the graph of nodes
def emitDec(b: Backend): String
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(that: Any): Boolean

Definition Classes
Module → AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
def findBinding(m: Node): Option[Binding]

A method to trace the graph of nodes backwards looking at inputs
A method to trace the graph of nodes backwards looking at inputs
m
Node to find bindings for
returns
nodes which have node m binded as their input
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getPathName(separator: String = "_"): String

separator
The separator to use for the path name
returns
the absolute path to a component instance from toplevel
def getPathName: String

returns
the absolute path to a component instance from toplevel
val hashCode: Int

Definition Classes
Module → AnyRef → Any
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
var moduleName: String

Name of the module this component generates (defaults to class name).
var name: String

Name of the instance.
var named: Boolean
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def nextIndex: Int
var nindex: Option[Int]
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
lazy val params: Parameters
var parent: Module
def printf(message: String, args: Node*): Unit

Adds a printf to the module called each clock cycle
Adds a printf to the module called each clock cycle
message
A c style sting to print out eg) %d, %x
args
Nodes whos data values should be printed
def reset: Bool

returns
the implied reset for this module
def reset_=(r: Bool): Unit
def setModuleName(n: String): Unit

Set the declaration name of the module to be string 'n'
def setName(n: String): Unit

Set the name of this module to the string 'n'
def stripComponent(s: String): String
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
Module → AnyRef → Any
var verilog_parameters: String
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
def wires: Array[(String, Bits)]

Get the I/O names and connections

Related Docs: object Module | package Chisel

abstract class Module extends AnyRef

Instance Constructors

new Module(_clock: Option[Clock] = None, _reset: Option[Bool] = None)

Type Members

type neededWireWraps = HashMap[StackTraceElement, ArrayBuffer[Data]]

Abstract Value Members

abstract def io: Data

Concrete Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

def <>(src: Module): Unit

final def ==(arg0: Any): Boolean

var _clock: Option[Clock]

def addClock(clock: Clock): Unit

def addDefaultReset: Unit

def addModule[T <: Module](c: ⇒ T)(implicit p: Parameters = params): T

def addModule[T <: Module](c: ⇒ T, f: PartialFunction[Any, Any]): T

def addPin[T <: Data](pin: T, name: String = ""): T

def addResetPin(r: Bool): Bool

def apply(name: String): Data

final def asInstanceOf[T0]: T0

def assert(cond: Bool, message: String): Unit

def bfs(visit: (Node) ⇒ Unit): Unit

val children: ArrayBuffer[Module]

def clock: Clock

def clone(): AnyRef

def debug(x: Node): Unit

def dfs(visit: (Node) ⇒ Unit): Unit

def emitDec(b: Backend): String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

def findBinding(m: Node): Option[Binding]

final def getClass(): Class[_]

def getPathName(separator: String = "_"): String

def getPathName: String

val hashCode: Int

final def isInstanceOf[T0]: Boolean

var moduleName: String

var name: String

var named: Boolean

final def ne(arg0: AnyRef): Boolean

def nextIndex: Int

var nindex: Option[Int]

final def notify(): Unit

final def notifyAll(): Unit

lazy val params: Parameters

var parent: Module

def printf(message: String, args: Node*): Unit

def reset: Bool

def reset_=(r: Bool): Unit

def setModuleName(n: String): Unit

def setName(n: String): Unit

def stripComponent(s: String): String

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

var verilog_parameters: String

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

def wires: Array[(String, Bits)]

Inherited from AnyRef

Inherited from Any

Ungrouped