Backend

abstract val keywords: Set[String]

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

val CC: String

val CCFLAGS: String

val CPPFLAGS: String

val CXX: String

val CXXFLAGS: String

val LDFLAGS: String

def W0Wtransform(): Unit

def addBindings: Unit

def addClocksAndResets: Unit

def addDefaultResets: Unit

val analyses: ArrayBuffer[(Module) ⇒ Unit]

final def asInstanceOf[T0]: T0

def asValidName(name: String): String

def assignClockAndResetToModules: Unit

def cc(dir: String, name: String, flags: String = "", isCC: Boolean = false): Unit

def checkModuleResolution: Unit

def checkPorts: Unit

val chiselENV: String

def clone(): AnyRef

def collectNodesIntoComp(mod: Module): Unit

def compile(c: Module, flags: Option[String] = None): Unit

def computeMemPorts(mod: Module): Unit

def connectResets: Unit

def copyToTarget(filename: String): Unit

def createOutputFile(name: String): FileWriter

def elaborate(c: Module): Unit

def emitDec(node: Node): String

def emitDef(node: Node): String

def emitRef(c: Module): String

def emitRef(node: Node): String

def emitTmp(node: Node): String

def ensureDir(dir: String): String

Ensures a directory *dir* exists on the filesystem.

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

def extractClassName(comp: Module): String

def finalize(): Unit

def findCombLoop: Unit

def findConsumers(mod: Module): Unit

def findGraphDims: (Int, Int, Int)

def flattenAll: Unit

def forceMatchingWidths: Unit

def fullyQualifiedName(m: Node): String

def gatherClocksAndResets: Unit

def genIndent(x: Int): String

Prints the call stack of Component as seen by the push/pop runtime.

final def getClass(): Class[_]

def hashCode(): Int

def inferAll(mod: Module): Int

def isBitsIo(node: Node, dir: IODirection): Boolean

Nodes which are created outside the execution trace from the toplevel component constructor (i.e.

def isEmittingComponents: Boolean

def isInObject(n: Node): Boolean

final def isInstanceOf[T0]: Boolean

def link(dir: String, target: String, objects: Seq[String], isCC: Boolean = false, isLib: Boolean = false): Unit

def lowerNodes(mod: Module): Unit

def markComponents: Unit

def nameAll(): Unit

def nameBindings: Unit

def nameRsts: Unit

val nameSpace: HashSet[String]

final def ne(arg0: AnyRef): Boolean

val needsLowering: Set[String]

final def notify(): Unit

final def notifyAll(): Unit

def printStack: Unit

def pruneUnconnectedIOs: Unit

def removeTypeNodes(mod: Module): Int

All classes inherited from Data are used to add type information and do not represent logic itself.

def renameNodes(nodes: Seq[Node], sep: String = "_"): Unit

Ensures each node such that it has a unique name across the whole hierarchy by prefixing its name by a component path (except for "reset" and all nodes in *c*).

def run(cmd: String): Boolean

def sortComponents: Unit

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

def topMod: Module

val transforms: ArrayBuffer[(Module) ⇒ Unit]

def verifyAllMuxes: Unit

def verifyComponents: Unit

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit