Chisel

FPGABackend

Related Doc: package Chisel

class FPGABackend extends VerilogBackend

class with no inline mem

Source
FPGA.scala
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  1. FPGABackend
  2. VerilogBackend
  3. Backend
  4. FileSystemUtilities
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Instance Constructors

  1. new FPGABackend()

Value Members

  1. final def !=(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any
  2. final def ##(): Int

    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any
  4. val CC: String

    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  5. val CCFLAGS: String

    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  6. val CPPFLAGS: String

    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  7. val CXX: String

    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  8. val CXXFLAGS: String

    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  9. val LDFLAGS: String

    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  10. def W0Wtransform(): Unit

    Definition Classes
    Backend
  11. def addBindings: Unit

    Definition Classes
    Backend
  12. def addClocksAndResets: Unit

    Definition Classes
    Backend
  13. def addDefaultResets: Unit

    Definition Classes
    Backend
  14. val analyses: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes
    Backend
  15. final def asInstanceOf[T0]: T0

    Definition Classes
    Any
  16. def asValidName(name: String): String

    Definition Classes
    Backend
  17. def assignClockAndResetToModules: Unit

    Definition Classes
    Backend
  18. def cc(dir: String, name: String, flags: String = "", isCC: Boolean = false): Unit

    Definition Classes
    FileSystemUtilities
  19. def checkModuleResolution: Unit

    Definition Classes
    Backend
  20. def checkPorts: Unit

    Definition Classes
    Backend
  21. val chiselENV: String

    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  22. def clone(): AnyRef

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  23. def collectNodesIntoComp(mod: Module): Unit

    Definition Classes
    Backend
  24. val compIndices: HashMap[String, Int]

    Definition Classes
    VerilogBackend
  25. def compile(c: Module, flags: Option[String]): Unit

    Definition Classes
    VerilogBackendBackend
  26. def computeMemPorts(mod: Module): Unit

    Definition Classes
    Backend
  27. def connectResets: Unit

    Definition Classes
    Backend
  28. def copyToTarget(filename: String): Unit

    Definition Classes
    FileSystemUtilities
  29. def createOutputFile(name: String): FileWriter

    Definition Classes
    FileSystemUtilities
  30. def doCompile(top: Module, out: FileWriter, depth: Int): Unit

    Definition Classes
    VerilogBackend
  31. def elaborate(c: Module): Unit

    Definition Classes
    VerilogBackendBackend
  32. def emitAssert(a: Assert): String

    Definition Classes
    VerilogBackend
  33. def emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[StringBuilder, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

    Definition Classes
    VerilogBackend
  34. def emitDec(node: Node): String

    Definition Classes
    VerilogBackendBackend
  35. def emitDecBase(node: Node, wire: String = "wire"): String

    Definition Classes
    VerilogBackend
  36. def emitDecReg(node: Node): String

    Definition Classes
    VerilogBackend
  37. def emitDecs(c: Module): StringBuilder

    Definition Classes
    VerilogBackend
  38. def emitDef(node: Node): String

    Definition Classes
    VerilogBackendBackend
  39. def emitDef(c: Module): StringBuilder

    Definition Classes
    VerilogBackend
  40. def emitDefs(c: Module): StringBuilder

    Definition Classes
    VerilogBackend
  41. def emitInit(node: Node): String

    Definition Classes
    VerilogBackend
  42. def emitInits(c: Module): StringBuilder

    Definition Classes
    VerilogBackend
  43. def emitModuleText(c: Module): StringBuilder

    Definition Classes
    VerilogBackend
  44. def emitPortDef(m: MemAccess, idx: Int): String

    Definition Classes
    VerilogBackend
  45. def emitPrintf(p: Printf): String

    Definition Classes
    VerilogBackend
  46. def emitRef(node: Node): String

    Definition Classes
    VerilogBackendBackend
  47. def emitRef(c: Module): String

    Definition Classes
    Backend
  48. def emitReg(node: Node): String

    Definition Classes
    VerilogBackend
  49. def emitRegs(c: Module): StringBuilder

    Definition Classes
    VerilogBackend
  50. def emitTmp(node: Node): String

    Definition Classes
    VerilogBackendBackend
  51. def emitWidth(node: Node): String

    Definition Classes
    VerilogBackend
  52. val emittedModules: HashSet[String]

    Definition Classes
    VerilogBackend
  53. def ensureDir(dir: String): String

    Ensures a directory *dir* exists on the filesystem.

    Ensures a directory *dir* exists on the filesystem.

    Definition Classes
    FileSystemUtilities
  54. final def eq(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef
  55. def equals(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any
  56. def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

    Definition Classes
    Backend
  57. def extractClassName(comp: Module): String

    Definition Classes
    Backend
  58. def finalize(): Unit

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  59. def findCombLoop: Unit

    Definition Classes
    Backend
  60. def findConsumers(mod: Module): Unit

    Definition Classes
    Backend
  61. def findGraphDims: (Int, Int, Int)

    Definition Classes
    Backend
  62. def flattenAll: Unit

    Definition Classes
    Backend
  63. def flushModules(defs: LinkedHashMap[String, LinkedHashMap[StringBuilder, ArrayBuffer[Module]]], level: Int): Unit

    Definition Classes
    VerilogBackend
  64. def forceMatchingWidths: Unit

    Definition Classes
    Backend
  65. def fullyQualifiedName(m: Node): String

    Definition Classes
    Backend
  66. def gatherClocksAndResets: Unit

    Definition Classes
    Backend
  67. def genHarness(c: Module, name: String): Unit

    Definition Classes
    VerilogBackend
  68. def genIndent(x: Int): String

    Prints the call stack of Component as seen by the push/pop runtime.

    Prints the call stack of Component as seen by the push/pop runtime.

    Attributes
    protected
    Definition Classes
    Backend
  69. final def getClass(): Class[_]

    Definition Classes
    AnyRef → Any
  70. def hashCode(): Int

    Definition Classes
    AnyRef → Any
  71. def inferAll(mod: Module): Int

    Definition Classes
    Backend
  72. def isBitsIo(node: Node, dir: IODirection): Boolean

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e.

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.

    This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Driver.nodes and Node.component).

    We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.

    Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

    Definition Classes
    Backend
  73. def isEmittingComponents: Boolean

    Definition Classes
    VerilogBackendBackend
  74. def isInObject(n: Node): Boolean

    Definition Classes
    Backend
  75. final def isInstanceOf[T0]: Boolean

    Definition Classes
    Any
  76. val keywords: Set[String]

    Definition Classes
    VerilogBackendBackend
  77. def link(dir: String, target: String, objects: Seq[String], isCC: Boolean = false, isLib: Boolean = false): Unit

    Definition Classes
    FileSystemUtilities
  78. def lowerNodes(mod: Module): Unit

    Definition Classes
    Backend
  79. def markComponents: Unit

    Definition Classes
    Backend
  80. val memConfs: HashMap[String, String]

    Definition Classes
    VerilogBackend
  81. def nameAll(): Unit

    Definition Classes
    Backend
  82. def nameBindings: Unit

    Definition Classes
    Backend
  83. def nameRsts: Unit

    Definition Classes
    Backend
  84. val nameSpace: HashSet[String]

    Definition Classes
    Backend
  85. final def ne(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef
  86. val needsLowering: Set[String]

    Definition Classes
    VerilogBackendBackend
  87. final def notify(): Unit

    Definition Classes
    AnyRef
  88. final def notifyAll(): Unit

    Definition Classes
    AnyRef
  89. def printStack: Unit

    Attributes
    protected
    Definition Classes
    Backend
  90. def pruneUnconnectedIOs: Unit

    Definition Classes
    Backend
  91. def removeTypeNodes(mod: Module): Int

    All classes inherited from Data are used to add type information and do not represent logic itself.

    All classes inherited from Data are used to add type information and do not represent logic itself.

    Definition Classes
    Backend
  92. def renameNodes(nodes: Seq[Node], sep: String = "_"): Unit

    Ensures each node such that it has a unique name across the whole hierarchy by prefixing its name by a component path (except for "reset" and all nodes in *c*).

    Ensures each node such that it has a unique name across the whole hierarchy by prefixing its name by a component path (except for "reset" and all nodes in *c*).

    Definition Classes
    Backend
  93. def run(cmd: String): Boolean

    Definition Classes
    FileSystemUtilities
  94. def sortComponents: Unit

    Definition Classes
    Backend
  95. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes
    AnyRef
  96. def synthesizeable(node: Node): Boolean

    Definition Classes
    VerilogBackend
  97. def toString(): String

    Definition Classes
    AnyRef → Any
  98. def topMod: Module

    Definition Classes
    Backend
  99. val transforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes
    Backend
  100. def verifyAllMuxes: Unit

    Definition Classes
    Backend
  101. def verifyComponents: Unit

    Definition Classes
    Backend
  102. final def wait(): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  103. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  104. final def wait(arg0: Long): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from VerilogBackend

Inherited from Backend

Inherited from FileSystemUtilities

Inherited from AnyRef

Inherited from Any

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