Chisel
Hardware module that is used to sequence n producers into 1 consumer.
Hardware module that is used to sequence n producers into 1 consumer. Priority is given to lower producer
val arb = Module(new Arbiter(2, UInt())) arb.io.in(0) <> producer0.io.out arb.io.in(1) <> producer1.io.out consumer.io.in <> arb.io.out
An I/O bundle for the Arbiter
Asynchronous Fifo.
Asynchronous Fifo. Used to cross two clock domains.
A class to create bit patterns Use the BitPat object instead of this class directly
Base class for built-in Chisel types Bits and SInt.
This class allows the connection to Verilog modules outside of chisel after generation
This class allows the connection to Verilog modules outside of chisel after generation
class DSP48E1 extends BlackBox { val io = new [[Chisel.Bundle Bundle]] // Create I/O with same as DSP val dspParams = new [[Chisel.VerilogParameters VerilogParameters]] // Create Parameters to be specified setVerilogParams(dspParams) renameClock("clk", "clock") renameReset("rst") // Implement functionality of DSP to allow simulation verification }
Defines a collection of datum of different types into a single coherent whole.
Create a new clock
Complex number representation create using the object Complex
Complex number representation create using the object Complex
val myNum = Complex[Fixed](Fixed(3, 16, 8), Fixed(1, 16, 8))
A counter module, can also be created using Counter
*Data* is part of the *Node* Composite Pattern class hierarchy.
*Data* is part of the *Node* Composite Pattern class hierarchy. It is the root of the type system which includes composites (Bundle, Vec) and atomic types (UInt, SInt, etc.). * Instances of Data are meant to help with construction and correctness of a logic graph. They will trimmed out of the graph before a *Backend* generates target code.
A double precision floating point representation Create using Dbl
An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'
An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'
val io = Decoupled(UInt(width=4)) io.valid := io.ready io.bits := UInt(5)
can be created using Decoupled
An I/O bundle for dequeuing data with valid/ready handshaking
An I/O bundle for enqueuing data with valid/ready handshaking
An I/O bundle for enqueuing data with valid/ready handshaking
val io = new EnqIO(UInt(width=5)) when (myCond) { io.enq(UInt(3)) }
class with no inline mem
A Fixed point data type
A 32 bit floating point representation class Create using the Flo object
Stores the actual value of a scala literal as a string.
Stores the actual value of a scala literal as a string. This class should not end-up being instantiated directly in user code.
Compute Log2 with truncation Use the Log2 object rather than this class directly
A class defining an Operator which has a output width log2 of the number of input bits
A tester to check a node graph from INPUTs to OUTPUTs directly
A Module or block to logically divide a hardware design
A Module or block to logically divide a hardware design
class MyModule extends Module { val io = new Bundle { val dataIn = UInt(INPUT, 4) val dataOut = UInt(OUTPUT, 4) } io.dataOut := io.dataIn } val myInst = Module(new MyModule) // create a MyModule
This is the same construct as module in verilog Also see Module object
Mux class defined as an operator
This trait allows an instantiation of something to be given a particular name
*Node* defines the root class of the class hierarchy for a [Composite Pattern](http://en.wikipedia.org/wiki/Composite_pattern).
*Node* defines the root class of the class hierarchy for a [Composite Pattern](http://en.wikipedia.org/wiki/Composite_pattern).
A digital logic graph is encoded as adjacency graph where instances of *Node* describe vertices and *inputs*, *consumers* member fields are used to traverse the directed graph respectively backward (from output to input) and forward (from input to output).
This trait enforces numerical properties on the data such as being able to add, subtract, multiply, divide etc
Converts a One Hot encoding to a UInt Use the OHToUInt object rather than this class directly
A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter.
A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter. Functionality is similar to ShiftRegister but this exposes a Pipe interface.
val pipe = new Pipe(UInt()) pipe.io.enq <> produce.io.out consumer.io.in <> pipe.io.deq
A class to detect the trailing bit Use the PriorityEncoder object rather than this class directly
A hardware module implementing a Queue
A hardware module implementing a Queue
the type of data to queue
val q = new Queue(UInt(), 16) q.io.enq <> producer.io.out consumer.io.in <> q.io.deq
An I/O Bundle for Queues
An I/O Bundle for Queues
the type of data to queue (such as UInt)
Class defining a ROM Use the ROM object rather than instantiating the ROM directly
ROMData stores the data for ROM
Class to read from ROM - internal, do not use
Hardware module that is used to sequence n producers into 1 consumer.
Hardware module that is used to sequence n producers into 1 consumer. Producers are chosen in round robin order.
val arb = new Module(RRArbiter(2, UInt()) arb.io.in(0) <> producer0.io.out arb.io.in(1) <> producer1.io.out consumer.io.in <> arb.io.out
If we have structured/aggregate types as top-level ports, we define suitable structures for encapsulating their components, in order to treat them as sc_fifo elements.
This class is the super class for test cases
This class is the super class for test cases
class myTest(c : TestModule) extends Tester(c) { ... }
An I/O Bundle containing data and a signal determining if it is valid
An I/O Bundle containing data and a signal determining if it is valid
myIO = Valid[UInt](UInt(width=4)) myIO.valid := Bool(true) myIO.bits := UInt(5)
can be constucted using the object Valid
This class enables the definition of verilog parameters without having to to string building
This class enables the definition of verilog parameters without having to to string building
class MyParams extends VerilogParameters { val MY_STR_PARAM = "FOO_BAR" val MY_INT_PARAM = 3 val MY_BOOL_PARAM = true }
This will generate a string
#( .MY_STR_PARAM("FOO_BAR"), .MY_INT_PARAM(3), .MY_BOOL_PARAM(1) )
Set these parameters with
setVerilogParameters(new MyParams)inside a BlackBox module or use
setVerilogParameters(myCustomString)
Version - dotted string with up to three components.
Version - dotted string with up to three components. Comparisons are done component by component for the smallest number of components. So: "3" >= "2.99.99" "3" < "4" "3" >= "3.99.99" "3.9" >= "3" "3.9" >= "3.0" "3.9" >= "3.9.99"
The empty string "" is the "maximum" version and compares > all other versions.
Create a new width
A class representing the when block Use when rather than this class directly
Compute the acos or inverse cos value of a Flo or Dbl returning the result in radians
Compute the asin or inverse sin value of a Flo or Dbl returning the result in radians
Compute the atan or inverse tan value of a Flo or Dbl returning the result in radians
Arbiter Control determining which producer has access
A bit pattern object to enable representation of dont cares
This object was generated by sbt-buildinfo.
This Singleton implements a log4j compatible interface.
This Singleton implements a log4j compatible interface. It is used through out the Chisel package to report errors and warnings detected at runtime.
Create a new Clock
Representation for complex numbers
Counter Object for Counter
Counter Object for Counter
val countOn = Bool(true) // increment counter every clock cycle val myCounter = Counter(8) when ( myCounter.inc() ) { ... // When counter value is max at 7 do something }
Create a 64 bit double precision floating point representation
Adds a ready-valid handshaking protocol to any interface
Adds a ready-valid handshaking protocol to any interface
the I/O can be 'flipped' so the data is INPUT instead using the function flip
DelayBetween works out the number of registers or delays for all possible directional paths between two nodes
An object for creating C style Enums
Fill fans out a Node to multiple copies
Factory methods for Fixed
Create a 32 bit floating point Object
Define the IODirection INPUT
linear feedback shift register
A factory for literal values
Compute Log2 with truncation of a UInt in hardware using a Mux Tree An alternative interpretation is it computes the minimum number of bits needed to represent x
Compute Log2 with truncation of a UInt in hardware using a Mux Tree An alternative interpretation is it computes the minimum number of bits needed to represent x
data_out := Log2(data_in)
Truncation is used so Log2(UInt(12412)) = 13
*seqRead* means that if a port tries to read the same address that another port is writing to in the same cycle, the read data is random garbage (from a LFSR, which returns "1" on its first invocation).
Methods to insert Modules into components correctly
A multiplexor which is a generalization of Mux to use nodes which aren't bools Mux uses this method internally If the values are not literals a Mux class is created and initialized
Implement a Multiplexor with a Bool A convienient wrapper for Multiplex
Builds a Mux tree out of the input signal vector using a one hot encoded select signal.
Builds a Mux tree out of the input signal vector using a one hot encoded select signal. Returns the output of the Mux tree.
MuxCase returns the first value that is enabled in a map of values
MuxLookup creates a cascade of n Muxs to search for a key value
Define the IODirection NODIR
NodeFill copys an instance of a Node multiple times or fans it out Any change to a Node such as setting inputs or changing width will is applied to all of them
Converts from One Hot Encoding to a UInt indicating which bit is active This is the inverse of UIntToOH
Define the IODirection OUTPUT
Similar to a shift register but with handshaking at start
Similar to a shift register but with handshaking at start
consumer.io.in := Pipe(producer.io.out, 2)
Returns the number of bits set (i.e value is 1) in the input signal.
Returns the number of bits set (i.e value is 1) in the input signal.
PopCount(UInt(29)) === UInt(4)
the bit position of the trailing 1 in the input vector with the assumption that multiple bits of the input bit vector can be set
data_out := PriorityEncoder(data_in)
Returns a bit vector in which only the least-significant 1 bit in the input vector, if any, is set.
Builds a Mux tree under the assumption that multiple select signals can be enabled.
Builds a Mux tree under the assumption that multiple select signals can be enabled. Priority is given to the first select signal.
the output of the Mux tree
Generic hardware queue.
Generic hardware queue. Required parameter entries controls the depth of the queues. The width of the queue is determined from the inputs.
consumer.io.in := Queue(producer.io.out, 16)
Read Only Memory object Optionally create in a map with integer addresses attached Create a Vec of literals rather than ROM directly
A register with an Enable signal
Litte/big bit endian conversion: reverse the order of the bits in a UInt.
Returns the n-cycle delayed version of the input signal.
the one hot encoding of the input UInt
val myOH = UIntToOH(UInt(5), 8) -> 0x20 val myOH2 = UIntToOH(UInt(0), 8) -> 0x01
Adds a valid protocol to any interface By default this creates a ValidIO class with valid and bits set to OUTPUT
Get the number of bits required
Chisel3 - Wrap a Chisel data type with a Wire.
Chisel3 - Wrap a Chisel data type with a Wire.
This sets the isWired state. It will be required for Chisel 3.0 The logic is:
Cast a node to be Bits
If there is an environment variable chiselArguments, construct an Array[String]
of its value split on ' ', otherwise, return a 0 length Array[String]
If there is an environment variable chiselArguments, construct an Array[String]
of its value split on ' ', otherwise, return a 0 length Array[String]
This makes it easy to merge with command line arguments and have the latter take precedence.
def main(args: Array[String]) { val readArgs(chiselEnvironmentArguments() ++ args) ... }
_chiselMain_ behaves as if it constructs an execution tree from the constructor of a sub class of Module which is passed as a parameter.
_chiselMain_ behaves as if it constructs an execution tree from the constructor of a sub class of Module which is passed as a parameter. That execution tree is simplified by aggregating all calls which are not constructors of a Module instance into the parent which is. The simplified tree (encoded through _Driver.children_) forms the basis of the generated verilog. Each node in the simplified execution tree is a _Module_ instance from which a verilog module is textually derived. As an optimization, _Backend_ classes output modules which are textually equivalent only once and update a _Module_ instance's _moduleName_ accordingly.
Compute the conjugate of a complex number using the function conj
Fold Right with a function
An object for separate cases in switch It is equivalent to a when block comparing to the condition Use outside of a switch statement is illegal
Usefulness is questionable, remove?
Check if an Integer is a power of 2
Compute the log2 rounded up
Compute the log2 rounded down with min value of 1
Compute the log2 rounded down
Compute the log2 rounded up with min value of 1
Conditional logic to form a switch block
Conditional logic to form a switch block
... // default values here switch ( myState ) { is( state1 ) { ... // some logic here } is( state2 ) { ... // some logic here } }
This is identical to when with the condition inverted
An object to create conditional logic See when for functions elsewhen and otherwise
An object to create conditional logic See when for functions elsewhen and otherwise
when ( myData === UInt(3) ) { ... // Some logic } .elsewhen ( myData === UInt(1) ) { ... // Some logic } .otherwise { ... // Some logic }