IRToWorkingIR
firrtl
IdentityLike
options
IdentityTransform
transforms
IgnoreInfo
Parser
IllegalAnalogDeclaration
CheckTypes
IllegalAttachExp
CheckTypes
IllegalChirrtlMemException
CheckHighForm
IllegalMemLatencyException
CheckHighFormLike
IllegalRenameException
RenameMap
IllegalResetType
CheckTypes
IllegalUnknownType
CheckTypes
Implicits
firrtl
IncP
PrimOps
IncorrectNumArgsException
CheckHighFormLike
IncorrectNumConstsException
CheckHighFormLike
Index
TargetToken fromIntToTargetToken
IndexNotUInt
CheckTypes
IndexOnNonVector
CheckTypes
IndexTooLarge
CheckTypes
Inequality
constraint
InferBinaryPoints
passes
InferBinaryPointsBenchmark
hot
InferReadWrite
memlib
InferReadWriteAnnotation
memlib
InferReadWritePass
memlib
InferResets
transforms
InferResetsException
InferResets
InferTypes
passes
InferWidths
passes
Info
ir LogLevel
InfoMap
ExpandWhens
InfoMode
Parser
InfoModeAnnotation
stage
InfoSerializer
JsonProtocol
Init
TargetToken
InlineAnnotation
passes
InlineBitExtractionsTransform
transforms
InlineCastsTransform
transforms
InlineInstances
passes
Input
ir
InputAnnotationFileAnnotation
options
InputConfigFileName
memlib
InstPath
TopWiringTransform
Instance
InstanceKey TargetToken fromDefInstanceToTargetToken fromStringToTargetToken fromWDefInstanceToTargetToken
InstanceGraph
analyses
InstanceKey
InstanceKeyGraph
InstanceKeyGraph
analyses
InstanceKind
firrtl
InstanceLoop
CheckHighFormLike
InstanceOfModuleMap
DuplicationHelper
InstanceTarget
annotations
InstanceTargetSerializer
JsonProtocol
IntParam
ir
IntWidth
ir
IntervalType
ir
InvalidAccessException
CheckHighFormLike
InvalidAnnotationFileException
annotations
InvalidAnnotationJSONException
annotations
InvalidConnect
CheckTypes
InvalidEscapeCharException
firrtl
InvalidLOCException
CheckHighFormLike
InvalidRange
CheckWidths
InvalidRegInit
CheckTypes
InvalidStringLitException
firrtl
IsAdd
constraint
IsComponent
annotations
IsDeclaration
ir
IsFloor
constraint
IsInvalid
ir
IsKnown
constraint
IsMax
constraint
IsMember
annotations
IsMemberSerializer
JsonProtocol
IsMin
constraint
IsModule
annotations
IsModuleSerializer
JsonProtocol
IsMul
constraint
IsNeg
constraint
IsPow
constraint
IsVar
constraint
id
FIRRTLParser Dependency
identityValue
FoldANDR FoldORR FoldXORR SimplifyReductionOp
ifdefDeclares
VerilogRender
ifdefInitials
VerilogRender
indent
Utils
index
WSubAccess ReferenceTarget SubAccess
inferRW
FirrtlExecutionOptions
inferReadWrite
InferReadWritePass
inferReadWriteStmt
InferReadWritePass
infer_mdir
CInferMDir
infer_mdir_e
CInferMDir
infer_mdir_s
CInferMDir
info
CDefMPort CDefMemory WDefInstance WDefInstanceConnector FIRRTLParser Attach Circuit Conditionally Connect DefInstance DefMemory DefModule DefNode DefRegister DefWire ExtModule FileInfo HasInfo IsInvalid Module PartialConnect Port Print Stop DefAnnotatedMemory Logger
infoMode
FirrtlExecutionOptions
infoModeName
FirrtlExecutionOptions FirrtlOptions
infos
MultiInfo
init
ReferenceTarget DefRegister
initialize
VerilogRender
initialize_mem
VerilogRender
initials
VerilogRender
inline
Utils
inlineTransform
Flatten
input
PassBenchmark TransformBenchmark
inputFile
PassBenchmark TransformBenchmark
inputFileName
ReplSeqMemAnnotation
inputFileNameOverride
FirrtlExecutionOptions
inputForm
ChirrtlToHighFirrtl DependencyAPIMigration FirrtlEmitter HighFirrtlToMiddleFirrtl IRToWorkingIR LowFirrtlOptimization MiddleFirrtlToLowFirrtl MinimumLowFirrtlOptimization ResolveAndCheck Transform VerilogEmitter SimpleTransform WrappedTransform IdentityTransform AnalyzeCircuit AnalyzeCircuit
inputState
PassBenchmark TransformBenchmark
inputSuffix
GroupAnnotation
inst
LogicNode
instOf
InstanceTarget IsModule ModuleTarget
instance
InstanceTarget
instdeclares
VerilogRender
int2WInt
Implicits
intLit
FIRRTLParser
internalTransform
IdentityLike Translator DeletedWrapper Compiler UpdateAnnotations
invalidAssign
VerilogRender
invalidateGraph
DependencyManager
invalidates
DependencyAPIMigration Transform DependencyAPI DependencyManager PreservesAll ExpandWhens ExpandWhensAndCheck InlineInstances LowerTypes PadWidths RemoveAccesses RemoveValidIf Uniquify ZeroWidth VerilogMemDelays WiringTransform FirrtlStage CatchExceptions WrappedTransform ConstantPropagation FlattenRegUpdate GroupAndDedup GroupComponents InferResets InlineCastsTransform RemoveReset TopWiringTransform
ir
firrtl
is
TargetToken
isBitExtract
Utils
isCast
Utils
isCircuitTarget
GenericTarget
isClassLoaded
ClassUtils
isCommandAvailable
FileUtils
isComplete
GenericTarget
isComponentTarget
GenericTarget
isLegal
GenericTarget
isLocal
CircuitTarget GenericTarget IsComponent ModuleTarget Target
isModuleTarget
GenericTarget
isOnly
Target
isTemp
Utils
isVCSAvailable
FileUtils