Type Members

1.  class AnnotationSeq extends AnyRef

   Container of all annotations for a Firrtl compiler

2.  case class CDefMPort(info: Info, name: String, tpe: Type, mem: String, exps: Seq[Expression], direction: MPortDir) extends Statement with Product with Serializable
3.  case class CDefMemory(info: Info, name: String, tpe: Type, size: Int, seq: Boolean) extends Statement with Product with Serializable
4.  class ChirrtlToHighFirrtl extends CoreTransform

   This transforms "CHIRRTL", the chisel3 IR, to "Firrtl".

   This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting circuit has only IR nodes, not WIR.

5.  sealed abstract class CircuitForm extends Ordered[CircuitForm]

   Current form of the Firrtl Circuit

   Current form of the Firrtl Circuit

   Form is a measure of addition restrictions on the legality of a Firrtl circuit. There is a notion of "highness" and "lowness" implemented in the compiler by extending scala.math.Ordered. "Lower" forms add additional restrictions compared to "higher" forms. This means that "higher" forms are strictly supersets of the "lower" forms. Thus, that any transform that operates on HighForm can also operate on MidForm or LowForm

6.  case class CircuitState(circuit: Circuit, form: CircuitForm, annotations: AnnotationSeq, renames: Option[RenameMap]) extends Product with Serializable

   Current State of the Circuit

   Current State of the Circuit

   circuit

   The current state of the Firrtl AST

   form

   The current form of the circuit

   annotations

   The current collection of Annotation

   renames

   A map of Named things that have been renamed. Generally only a return value from Transforms

7.  case class CommonOptions(topName: String = "", targetDirName: String = ".", globalLogLevel: logger.LogLevel.Value = LogLevel.None, logToFile: Boolean = false, logClassNames: Boolean = false, classLogLevels: Map[String, logger.LogLevel.Value] = Map.empty, programArgs: Seq[String] = Seq.empty) extends ComposableOptions with Product with Serializable

   Most of the chisel toolchain components require a topName which defines a circuit or a device under test.

   Most of the chisel toolchain components require a topName which defines a circuit or a device under test. Much of the work that is done takes place in a directory. It would be simplest to require topName to be defined but in practice it is preferred to defer this. For example, in chisel, by deferring this it is possible for the execute there to first elaborate the circuit and then set the topName from that if it has not already been set.

8.  trait Compiler extends LazyLogging
9.  trait ComposableOptions extends AnyRef

   Use this trait to define an options class that can add its private command line options to a externally declared parser.

   Use this trait to define an options class that can add its private command line options to a externally declared parser. NOTE In all derived trait/classes, if you intend on maintaining backwards compatibility, be sure to add new options at the end of the current ones and don't remove any existing ones.

10.  trait Constraint extends AnyRef
11.  sealed abstract class CoreTransform extends SeqTransform
12.  case class EmitAllModulesAnnotation(emitter: Class[_ <: Emitter]) extends EmitAnnotation with Product with Serializable
13.  sealed trait EmitAnnotation extends NoTargetAnnotation
14.  case class EmitCircuitAnnotation(emitter: Class[_ <: Emitter]) extends EmitAnnotation with Product with Serializable
15.  sealed trait EmittedAnnotation[T <: EmittedComponent] extends NoTargetAnnotation

    Traits for Annotations containing emitted components

16.  sealed abstract class EmittedCircuit extends EmittedComponent
17.  sealed trait EmittedCircuitAnnotation[T <: EmittedCircuit] extends EmittedAnnotation[T]
18.  sealed abstract class EmittedComponent extends AnyRef
19.  final case class EmittedFirrtlCircuit(name: String, value: String) extends EmittedCircuit with Product with Serializable
20.  case class EmittedFirrtlCircuitAnnotation(value: EmittedFirrtlCircuit) extends EmittedCircuitAnnotation[EmittedFirrtlCircuit] with Product with Serializable
21.  final case class EmittedFirrtlModule(name: String, value: String) extends EmittedModule with Product with Serializable
22.  case class EmittedFirrtlModuleAnnotation(value: EmittedFirrtlModule) extends EmittedModuleAnnotation[EmittedFirrtlModule] with Product with Serializable
23.  sealed abstract class EmittedModule extends EmittedComponent
24.  sealed trait EmittedModuleAnnotation[T <: EmittedModule] extends EmittedAnnotation[T]
25.  final case class EmittedVerilogCircuit(name: String, value: String) extends EmittedCircuit with Product with Serializable
26.  case class EmittedVerilogCircuitAnnotation(value: EmittedVerilogCircuit) extends EmittedCircuitAnnotation[EmittedVerilogCircuit] with Product with Serializable
27.  final case class EmittedVerilogModule(name: String, value: String) extends EmittedModule with Product with Serializable
28.  case class EmittedVerilogModuleAnnotation(value: EmittedVerilogModule) extends EmittedModuleAnnotation[EmittedVerilogModule] with Product with Serializable
29.  trait Emitter extends Transform

    Defines old API for Emission.

    Defines old API for Emission. Deprecated

30.  case class EmitterException(message: String) extends PassException with Product with Serializable
31.  class ExecutionOptionsManager extends HasParser with HasCommonOptions

32.  case class ExpWidth(arg1: Width) extends Width with HasMapWidth with Product with Serializable
33.  class FIRRTLException extends RuntimeException
34.  sealed abstract class FirrtlEmitter extends Transform with Emitter
35.  case class FirrtlExecutionFailure(message: String) extends FirrtlExecutionResult with Product with Serializable

    The firrtl compilation failed.

    The firrtl compilation failed.

    message

    Some kind of hint as to what went wrong.

36.  case class FirrtlExecutionOptions(inputFileNameOverride: String = "", outputFileNameOverride: String = "", compilerName: String = "verilog", infoModeName: String = "append", inferRW: Seq[String] = Seq.empty, firrtlSource: Option[String] = None, customTransforms: Seq[Transform] = List.empty, annotations: List[Annotation] = List.empty, annotationFileNameOverride: String = "", outputAnnotationFileName: String = "", emitOneFilePerModule: Boolean = false, dontCheckCombLoops: Boolean = false, noDCE: Boolean = false, annotationFileNames: List[String] = List.empty, firrtlCircuit: Option[Circuit] = None) extends ComposableOptions with Product with Serializable

    The options that firrtl supports in callable component sense

    The options that firrtl supports in callable component sense

    inputFileNameOverride

    default is targetDir/topName.fir

    outputFileNameOverride

    default is targetDir/topName.v the .v is based on the compilerName parameter

    compilerName

    which compiler to use

    annotations

    annotations to pass to compiler

37.  sealed trait FirrtlExecutionResult extends AnyRef
38.  class FirrtlExecutionSuccess extends FirrtlExecutionResult

    Indicates a successful execution of the firrtl compiler, returning the compiled result and the type of compile

39.  trait Gender extends AnyRef
40.  trait HasCommonOptions extends AnyRef
41.  trait HasFirrtlOptions extends AnyRef
42.  abstract class HasParser extends AnyRef
43.  class HighFirrtlCompiler extends Compiler

    Emits input circuit Will replace Chirrtl constructs with Firrtl

44.  class HighFirrtlEmitter extends FirrtlEmitter
45.  class HighFirrtlToMiddleFirrtl extends CoreTransform

    Expands aggregate connects, removes dynamic accesses, and when statements.

    Expands aggregate connects, removes dynamic accesses, and when statements. Checks for uninitialized values. Must accept a well-formed graph. Operates on working IR nodes.

46.  class IRToWorkingIR extends CoreTransform

    Converts from the bare intermediate representation (ir.scala) to a working representation (WIR.scala)

47.  case class InvalidEscapeCharException(message: String) extends ParserException with Product with Serializable
48.  case class InvalidStringLitException(message: String) extends ParserException with Product with Serializable
49.  trait Kind extends AnyRef
50.  abstract class LexerHelper extends AnyRef
51.  class LowFirrtlCompiler extends Compiler

    Emits lowered input circuit

52.  class LowFirrtlEmitter extends FirrtlEmitter
53.  class LowFirrtlOptimization extends CoreTransform

    Runs a series of optimization passes on LowFirrtl

    Runs a series of optimization passes on LowFirrtl

    Note

    This is currently required for correct Verilog emission TODO Fix the above note

54.  abstract class MPortDir extends FirrtlNode
55.  case class MaxWidth(args: Seq[Width]) extends Width with HasMapWidth with Product with Serializable
56.  class MemoizedHash[T] extends AnyRef
57.  class MiddleFirrtlCompiler extends Compiler

    Emits middle Firrtl input circuit

58.  class MiddleFirrtlEmitter extends FirrtlEmitter
59.  class MiddleFirrtlToLowFirrtl extends CoreTransform

    Expands all aggregate types into many ground-typed components.

    Expands all aggregate types into many ground-typed components. Must accept a well-formed graph of only middle Firrtl features. Operates on working IR nodes.

60.  case class MinWidth(args: Seq[Width]) extends Width with HasMapWidth with Product with Serializable
61.  case class MinusWidth(arg1: Width, arg2: Width) extends Width with HasMapWidth with Product with Serializable
62.  class ModuleGraph extends AnyRef

    Maintains a one to many graph of each modules instantiated child module.

    Maintains a one to many graph of each modules instantiated child module. This graph can be searched for a path from a child module back to one of it's parents. If one is found a recursive loop has happened The graph is a map between the name of a node to set of names of that nodes children

63.  class Namespace extends AnyRef
64.  final case class OneFilePerModule(targetDir: String) extends OutputConfig with Product with Serializable
65.  sealed abstract class OutputConfig extends AnyRef

    Firrtl output configuration specified by FirrtlExecutionOptions

    Firrtl output configuration specified by FirrtlExecutionOptions

    Derived from the fields of the execution options

    See also

    FirrtlExecutionOptions.getOutputConfig

66.  case class ParameterNotSpecifiedException(message: String) extends ParserException with Product with Serializable
67.  case class ParameterRedefinedException(message: String) extends ParserException with Product with Serializable
68.  class ParserException extends FIRRTLException
69.  case class PlusWidth(arg1: Width, arg2: Width) extends Width with HasMapWidth with Product with Serializable
70.  final class RenameMap extends AnyRef

    Map old names to new names

    Map old names to new names

    Transforms that modify names should return a RenameMap with the CircuitState These are mutable datastructures for convenience

71.  class ResolveAndCheck extends CoreTransform

    Resolves types, kinds, and genders, and checks the circuit legality.

    Resolves types, kinds, and genders, and checks the circuit legality. Operates on working IR nodes and high Firrtl.

72.  abstract class SeqTransform extends Transform with SeqTransformBased

    For transformations that are simply a sequence of transforms

73.  trait SeqTransformBased extends AnyRef
74.  final case class SingleFile(targetFile: String) extends OutputConfig with Product with Serializable
75.  case class SyntaxErrorsException(message: String) extends ParserException with Product with Serializable
76.  case class TargetDirAnnotation(value: String) extends NoTargetAnnotation with Product with Serializable

    Annotation that contains the CommonOptions target directory

77.  abstract class Transform extends LazyLogging

    The basic unit of operating on a Firrtl AST

78.  case class VRandom(width: BigInt) extends Expression with Product with Serializable
79.  case class VarWidth(name: String) extends Width with HasMapWidth with Product with Serializable
80.  class VerilogCompiler extends Compiler

    Emits Verilog

81.  class VerilogEmitter extends SeqTransform with Emitter
82.  class Visitor extends FIRRTLBaseVisitor[FirrtlNode]
83.  case class WDefInstance(info: Info, name: String, module: String, tpe: Type) extends Statement with IsDeclaration with Product with Serializable
84.  case class WDefInstanceConnector(info: Info, name: String, module: String, tpe: Type, portCons: Seq[(Expression, Expression)]) extends Statement with IsDeclaration with Product with Serializable
85.  class WGeq extends Constraint
86.  case class WRef(name: String, tpe: Type, kind: Kind, gender: Gender) extends Expression with Product with Serializable
87.  case class WSubAccess(expr: Expression, index: Expression, tpe: Type, gender: Gender) extends Expression with Product with Serializable
88.  case class WSubField(expr: Expression, name: String, tpe: Type, gender: Gender) extends Expression with Product with Serializable
89.  case class WSubIndex(expr: Expression, value: Int, tpe: Type, gender: Gender) extends Expression with Product with Serializable
90.  class WrappedExpression extends AnyRef
91.  class WrappedType extends AnyRef
92.  class WrappedWidth extends AnyRef