BitVector Bits SInt UInt AnalogDriver AnalogDriverBitVector AnalogDriverEnum BinaryMultiplexer BinaryMultiplexerEnum BinaryMultiplexerWidthable BinaryOperator BinaryOperatorWidthableInputs Cast CastBitVectorToBitVector CastBitsToEnum CastEnumToBits CastEnumToEnum ConstantOperator ConstantOperatorWidthableInputs Multiplexer MultiplexerEnum MultiplexerWidthable andR orR xorR Equal EqualSim NotEqual PastBitvector PastEnum UnaryOperator UnaryOperatorWidthableInputs

BigIntBuilder IntBuilder

BigDecimalBuilder DoubleBuilder IntBuilder

internals

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core

fiber

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BigIntBuilder IntBuilder

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sim

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internals

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UnionElement

Tab2 Tab4 VerilogTheme

VecBuilder

AFix Num SInt SpinalLog UInt

core

core

core

BitVector

BitVector

BitVector

AssignmentStatement SuffixExpression

SpinalConfig

PhaseVerilog

PrePopTask

Fiber

Ram_2c_1w_1rs

Mem Ram_1w_1ra Ram_1w_1rs Ram_1wrs Ram_2wrs

MemTechnologyKind auto distributedLut ramBlock registerFile

AsyncThread

SimCompiled

SpinalGhdlBackendConfig SpinalIVerilogBackendConfig SpinalVCSBackendConfig SpinalVerilatorBackendConfig SpinalVpiBackendConfig

DefaultTag

VerilogBase

RetainerGroup

Interface

MemReadBufferTag

Interface

Interface

Interface

sim SpinalGhdlBackendConfig SpinalIVerilogBackendConfig SpinalVCSBackendConfig SpinalVerilatorBackendConfig SpinalVpiBackendConfig SpinalXSimBackendConfig

sim

SymbiYosysFormalBackendConfig

AFix SIntPimper UIntPimper

DataAnalyzer ModuleAnalyzer

AssignedRange

PhysicalNumber SimAFixPimper SimFix SimSFixPimper SimUFixPimper

MaskedLiteral AssignedRange SimBaseTypePimper SimBitVectorPimper SimProxy SimProxy

AssignedBits

ScopeProperty

IntPimped SimBoolPimper SimProxy SimProxy

SimBitVectorPimper

SimBaseTypePimper SimBigIntPimper SimBitVectorPimper

Bits

PhysicalNumber SimAFixPimper SimFix

SimEnumPimper

TimeNumber

ImplicitArea

PhysicalNumber BooleanPimped SimBitVectorPimper SimProxy SimBoolPimper SimProxy

Data

PhysicalNumber SimBitVectorPimper SimProxy

AFix Data XFix

SFixCast SIntPimper

SFix

AFix Area Attribute BaseType BitVector Bundle ClockDomain ClockDomainReportTag ClockDomainTag MaskedLiteral Mem Nameable QFormat SFix Vec AsyncThread Handle AssignmentStatement BinaryMultiplexerWidthable BitAssignmentFixed BitAssignmentFloating BitVectorLiteral BitsLiteral CastBitVectorToBitVector Expression MultiplexerWidthable Add And Div Mod Mul Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Sub Xor RangedAssignmentFixed RangedAssignmentFloating SIntLiteral UIntLiteral

BigIntBuilder

AnalogDriver BaseNode BinaryOperator BitVectorBitAccessFixed BitVectorBitAccessFloating

Expression

HertzNumber

Pull

UFixCast UIntPimper

UFix

ScopeProperty

BoolEdges

Bool

BoolEdges

core

PhaseContext

Component GlobalData SpinalReport

SpinalReport SymbiYosysFormalBackendConfig

Ram_Generic

Component

Component

Component

SimpComponentPimper

Verilator

Verilator

SpinalConfig

MemBlackboxingPolicy blackboxAll blackboxAllWhatsYouCan blackboxByteEnables blackboxOnlyIfRequested blackboxRequestedAndUninferable

AssertStatement

AFix Num SInt UInt

AFix

AFix SFix2D UFix2D XFix

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SInt UInt

SpinalStruct