Value Members

1.  final def !=(arg0: Any): Boolean

   Definition Classes

   AnyRef → Any

2.  final def ##(): Int

   Definition Classes

   AnyRef → Any

3.  final def ==(arg0: Any): Boolean

   Definition Classes

   AnyRef → Any

4.  lazy val TestDirectory: File

   Definition Classes

   BackendCompilationUtilities

5.  final def asInstanceOf[T0]: T0

   Definition Classes

   Any

6.  val chiselVersionString: String
7.  def clone(): AnyRef

   Attributes

   protected[lang]

   Definition Classes

   AnyRef

   Annotations

   @throws( ... ) @native()

8.  def compileFirrtlToVerilog(prefix: String, dir: File): Boolean

   Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM

   Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM

   prefix

   basename of the file

   dir

   directory where file lives

   returns

   true if compiler completed successfully

   Definition Classes

   BackendCompilationUtilities

9.  def copyResourceToFile(name: String, file: File): Unit

   Definition Classes

   BackendCompilationUtilities

10.  def cppToExe(prefix: String, dir: File): ProcessBuilder

    Definition Classes

    BackendCompilationUtilities

11.  def createTestDirectory(testName: String): File

    Definition Classes

    BackendCompilationUtilities

12.  def dumpAnnotations(ir: Circuit, optName: Option[File]): File

    Emit the annotations of a circuit

    Emit the annotations of a circuit

    ir

    The circuit containing annotations to be emitted

    optName

    An optional filename (will use s"${ir.name}.json" otherwise)

13.  def dumpFirrtl(ir: Circuit, optName: Option[File]): File

    Dump the elaborated Chisel IR Circuit as a FIRRTL String, without invoking FIRRTL.

    Dump the elaborated Chisel IR Circuit as a FIRRTL String, without invoking FIRRTL.

    If no File is given as input, it will dump to a default filename based on the name of the top Module.

    optName

    File to dump to. If unspecified, defaults to "<topmodule>.fir".

    returns

    The File the circuit was dumped to.

14.  def dumpProto(c: Circuit, optFile: Option[File]): File

    Dump the elaborated Circuit to ProtoBuf.

    Dump the elaborated Circuit to ProtoBuf.

    If no File is given as input, it will dump to a default filename based on the name of the top Module.

    c

    Elaborated Chisel Circuit.

    optFile

    Optional File to dump to. If unspecified, defaults to "<topmodule>.pb".

    returns

    The File the circuit was dumped to.

15.  def elaborate[T <: RawModule](gen: () ⇒ T): Circuit

    Elaborate the Module specified in the gen function into a Chisel IR Circuit.

    Elaborate the Module specified in the gen function into a Chisel IR Circuit.

    gen

    A function that creates a Module hierarchy.

    returns

    The resulting Chisel IR in the form of a Circuit. (TODO: Should be FIRRTL IR)

16.  def emit[T <: RawModule](ir: Circuit): String

    Emit the given Chisel IR Circuit as a FIRRTL string, without invoking FIRRTL.

    Emit the given Chisel IR Circuit as a FIRRTL string, without invoking FIRRTL.

    ir

    Chisel IR Circuit, generated e.g. by elaborate().

17.  def emit[T <: RawModule](gen: () ⇒ T): String

    Emit the Module specified in the gen function directly as a FIRRTL string without invoking FIRRTL.

    Emit the Module specified in the gen function directly as a FIRRTL string without invoking FIRRTL.

    gen

    A function that creates a Module hierarchy.

18.  def emitVerilog[T <: RawModule](gen: ⇒ T): String

    Elaborate the Module specified in the gen function into Verilog.

    Elaborate the Module specified in the gen function into Verilog.

    gen

    A function that creates a Module hierarchy.

    returns

    A String containing the design in Verilog.

19.  final def eq(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

20.  def equals(arg0: Any): Boolean

    Definition Classes

    AnyRef → Any

21.  def execute(args: Array[String], dut: () ⇒ RawModule): ChiselExecutionResult

    Run the chisel3 compiler and possibly the firrtl compiler with options specified via an array of Strings

    Run the chisel3 compiler and possibly the firrtl compiler with options specified via an array of Strings

    args

    The options specified, command line style

    dut

    The device under test

    returns

    An execution result with useful stuff, or failure with message

22.  def execute(optionsManager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions, dut: () ⇒ RawModule): ChiselExecutionResult

    Run the chisel3 compiler and possibly the firrtl compiler with options specified

    Run the chisel3 compiler and possibly the firrtl compiler with options specified

    optionsManager

    The options specified

    dut

    The device under test

    returns

    An execution result with useful stuff, or failure with message

23.  def executeExpectingFailure(prefix: String, dir: File, assertionMsg: String): Boolean

    Definition Classes

    BackendCompilationUtilities

24.  def executeExpectingSuccess(prefix: String, dir: File): Boolean

    Definition Classes

    BackendCompilationUtilities

25.  def finalize(): Unit

    Attributes

    protected[lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

26.  def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder

    Definition Classes

    BackendCompilationUtilities

27.  final def getClass(): Class[_]

    Definition Classes

    AnyRef → Any

    Annotations

    @native()

28.  def hashCode(): Int

    Definition Classes

    AnyRef → Any

    Annotations

    @native()

29.  final def isInstanceOf[T0]: Boolean

    Definition Classes

    Any

30.  def main(args: Array[String]): Unit

    This is just here as command line way to see what the options are It will not successfully run TODO: Look into dynamic class loading as way to make this main useful

    This is just here as command line way to see what the options are It will not successfully run TODO: Look into dynamic class loading as way to make this main useful

    args

    unused args

31.  def makeHarness(template: (String) ⇒ String, post: String)(f: File): File

    Definition Classes

    BackendCompilationUtilities

32.  final def ne(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

33.  final def notify(): Unit

    Definition Classes

    AnyRef

    Annotations

    @native()

34.  final def notifyAll(): Unit

    Definition Classes

    AnyRef

    Annotations

    @native()

35.  def parseArgs(args: Array[String]): Unit
36.  final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes

    AnyRef

37.  def targetDir(): String
38.  def timeStamp: String

    Definition Classes

    BackendCompilationUtilities

39.  def toFirrtl(ir: Circuit): Circuit

    Convert the given Chisel IR Circuit to a FIRRTL Circuit.

    Convert the given Chisel IR Circuit to a FIRRTL Circuit.

    ir

    Chisel IR Circuit, generated e.g. by elaborate().

40.  def toString(): String

    Definition Classes

    AnyRef → Any

41.  def verilogToCpp(dutFile: String, dir: File, vSources: Seq[File], cppHarness: File, suppressVcd: Boolean, resourceFileName: String): ProcessBuilder

    Definition Classes

    BackendCompilationUtilities

42.  val version: String
43.  final def wait(): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

44.  final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

45.  final def wait(arg0: Long): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... ) @native()

46.  def yosysExpectFailure(customTop: String, referenceTop: String, testDir: File, resets: Seq[(Int, String, Int)]): Boolean

    Definition Classes

    BackendCompilationUtilities

47.  def yosysExpectSuccess(customTop: String, referenceTop: String, testDir: File, resets: Seq[(Int, String, Int)]): Boolean

    Definition Classes

    BackendCompilationUtilities