Packages

class ChiselStage extends Stage

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Inherited
  1. ChiselStage
  2. Stage
  3. Phase
  4. DependencyAPI
  5. TransformLike
  6. LazyLogging
  7. AnyRef
  8. Any
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Visibility
  1. Public
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Instance Constructors

  1. new ChiselStage()

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  5. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  6. final def emitChirrtl(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String

    Convert a Chisel module to a CHIRRTL string

    Convert a Chisel module to a CHIRRTL string

    gen

    a call-by-name Chisel module

    args

    additional command line arguments to pass to Chisel param annotations additional annotations to pass to Chisel

    returns

    a string containing the Verilog output

  7. final def emitFirrtl(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String

    Convert a Chisel module to a FIRRTL string

    Convert a Chisel module to a FIRRTL string

    gen

    a call-by-name Chisel module

    args

    additional command line arguments to pass to Chisel param annotations additional annotations to pass to Chisel

    returns

    a string containing the FIRRTL output

  8. final def emitSystemVerilog(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String

    Convert a Chisel module to SystemVerilog

    Convert a Chisel module to SystemVerilog

    gen

    a call-by-name Chisel module

    args

    additional command line arguments to pass to Chisel param annotations additional annotations to pass to Chisel

    returns

    a string containing the SystemVerilog output

  9. final def emitVerilog(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String

    Convert a Chisel module to Verilog

    Convert a Chisel module to Verilog

    gen

    a call-by-name Chisel module

    args

    additional command line arguments to pass to Chisel param annotations additional annotations to pass to Chisel

    returns

    a string containing the Verilog output

  10. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  11. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  12. final def execute(args: Array[String], annotations: AnnotationSeq): AnnotationSeq
    Definition Classes
    Stage
  13. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  14. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  15. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  16. def invalidates(a: Phase): Boolean
    Definition Classes
    ChiselStage → DependencyAPI
  17. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  18. val logger: Logger
    Attributes
    protected
    Definition Classes
    LazyLogging
  19. lazy val name: String
    Definition Classes
    Phase → TransformLike
  20. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  21. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  22. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  23. def optionalPrerequisiteOf: Seq[Nothing]
    Definition Classes
    ChiselStage → DependencyAPI
  24. def optionalPrerequisites: Seq[Nothing]
    Definition Classes
    ChiselStage → DependencyAPI
  25. final lazy val phaseManager: ChiselPhase
  26. def prerequisites: Seq[Nothing]
    Definition Classes
    ChiselStage → DependencyAPI
  27. def run(annotations: AnnotationSeq): AnnotationSeq
    Definition Classes
    ChiselStage → Stage
  28. val shell: Shell
    Definition Classes
    ChiselStage → Stage
  29. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  30. val targets: Seq[PhaseDependency]
  31. def toString(): String
    Definition Classes
    AnyRef → Any
  32. final def transform(annotations: AnnotationSeq): AnnotationSeq
    Definition Classes
    Stage → TransformLike
  33. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  34. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  35. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()

Deprecated Value Members

  1. def dependents: Seq[Dependency[Phase]]
    Definition Classes
    DependencyAPI
    Annotations
    @deprecated
    Deprecated

    (Since version FIRRTL 1.3) Due to confusion, 'dependents' is being renamed to 'optionalPrerequisiteOf'. Override the latter instead.

Inherited from Stage

Inherited from Phase

Inherited from DependencyAPI[Phase]

Inherited from TransformLike[AnnotationSeq]

Inherited from LazyLogging

Inherited from AnyRef

Inherited from Any

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