trait LFSR extends PRNG
Trait that defines a Linear Feedback Shift Register (LFSR).
If the user specifies a seed, then a compile-time check is added that they are not initializing the LFSR to a state which will cause it to lock up. If the user does not set a seed, then the least significant bit of the state will be set or reset based on the choice of reduction operator.
Linear Supertypes
Known Subclasses
Type Hierarchy
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Inherited
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def
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final
def
##(): Int
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final
def
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def
IO[T <: Data](iodef: T): T
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def
_bindIoInPlace(iodef: Data): Unit
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var
_closed: Boolean
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def
_compatAutoWrapPorts(): Unit
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def
_compatIoPortBound(): Boolean
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final
def
asInstanceOf[T0]: T0
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def
circuitName: String
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final
val
clock: Clock
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def
clone(): AnyRef
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val
compileOptions: CompileOptions
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def
computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]
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def
desiredName: String
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(that: Any): Boolean
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def
finalize(): Unit
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def
getClass(): Class[_]
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def
getCommands: Seq[Command]
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def
getIds: Seq[HasId]
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def
getModulePorts: Seq[Data]
- Attributes
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lazy val
getPorts: Seq[Port]
- Definition Classes
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def
hasSeed: Boolean
- Definition Classes
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def
hashCode(): Int
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def
instanceName: String
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val
io: PRNGIO
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final
def
isInstanceOf[T0]: Boolean
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final
lazy val
name: String
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def
nameIds(rootClass: Class[_]): HashMap[HasId, String]
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final
def
ne(arg0: AnyRef): Boolean
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final
def
nextState(s: Seq[Bool]): Seq[Bool]
The method that will be used to update the state of this PRNG
The method that will be used to update the state of this PRNG
- s
input state
- returns
the next state after
stepapplications of PRNG.delta
- Definition Classes
- PRNG
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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var
override_clock: Option[Clock]
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var
override_reset: Option[Bool]
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def
parentModName: String
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def
parentPathName: String
- Definition Classes
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def
pathName: String
- Definition Classes
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def
portsContains(elem: Data): Boolean
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- protected
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def
portsSize: Int
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- protected
- Definition Classes
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final
val
reset: Reset
- Definition Classes
- MultiIOModule
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def
resetValue: Vec[Bool]
Allow implementations to override the reset value, e.g., if some bits should be don't-cares.
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val
seed: Option[BigInt]
- Definition Classes
- PRNG
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def
suggestName(seed: ⇒ String): LFSR.this.type
- Definition Classes
- HasId
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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final
def
toAbsoluteTarget: IsModule
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final
def
toNamed: ModuleName
- Definition Classes
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def
toString(): String
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final
def
toTarget: ModuleTarget
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
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final
def
wait(arg0: Long): Unit
- Definition Classes
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- @throws( ... ) @native()
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val
width: Int
- Definition Classes
- PRNG
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,FixedPoint,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.