object RenameAnnotatedMemoryPorts extends Transform with Pass
Changes memory port names to standard port names (i.e. RW0 instead T_408)
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def
createMemProto(m: DefAnnotatedMemory): DefAnnotatedMemory
Renames memory ports to a standard naming scheme:
Renames memory ports to a standard naming scheme:
- R0, R1, ... for each read port
- W0, W1, ... for each write port
- RW0, RW1, ... for each readwrite port
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execute(state: CircuitState): CircuitState
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
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Input Firrtl AST
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A transformed Firrtl AST
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def
getMemPortMap(m: DefAnnotatedMemory, memPortMap: MemPortMap): Unit
Maps the serialized form of all memory port field names to the corresponding new memory port field Expression.
Maps the serialized form of all memory port field names to the corresponding new memory port field Expression. E.g.:
- ("m.read.addr") becomes (m.R0.addr)
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inputForm: CircuitForm
The firrtl.CircuitForm that this transform requires to operate on
The firrtl.CircuitForm that this transform requires to operate on
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logger: Logger
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name: String
A convenience function useful for debugging and error messages
A convenience function useful for debugging and error messages
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outputForm: CircuitForm
The firrtl.CircuitForm that this transform outputs
The firrtl.CircuitForm that this transform outputs
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def
run(c: Circuit): Circuit
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- RenameAnnotatedMemoryPorts → Pass
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final
def
runTransform(state: CircuitState): CircuitState
Perform the transform and update annotations.
Perform the transform and update annotations.
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Input Firrtl AST
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A transformed Firrtl AST
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transform(state: CircuitState): CircuitState
A mathematical transform on some type
A mathematical transform on some type
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an output object of the same type
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def
updateMemMods(m: DefModule): DefModule
Replaces candidate memories and their references with standard port names
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def
updateMemStmts(memPortMap: MemPortMap)(s: Statement): Statement
Replaces candidate memories with memories with standard port names Does not update the references (this is done via updateStmtRefs)
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def
getMyAnnotations(state: CircuitState): Seq[Annotation]
Convenience method to get annotations relevant to this Transform
Convenience method to get annotations relevant to this Transform
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The CircuitState form which to extract annotations
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A collection of annotations
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(Since version 1.1) Just collect the actual Annotation types the transform wants
This is the documentation for Firrtl.