Packages

p

firrtl

passes

package passes

Ordering
  1. Alphabetic
Visibility
  1. Public
  2. All

Type Members

  1. trait CheckHighFormLike extends AnyRef
  2. case class DataRef(exp: Expression, male: String, female: String, mask: String, rdwrite: Boolean) extends Product with Serializable
  3. class Errors extends AnyRef
  4. class InferWidths extends Transform with ResolvedAnnotationPaths
  5. case class InlineAnnotation(target: Named) extends SingleTargetAnnotation[Named] with Product with Serializable

    Indicates that something should be inlined

  6. class InlineInstances extends Transform with RegisteredTransform

    Inline instances as indicated by existing InlineAnnotations

    Inline instances as indicated by existing InlineAnnotations

    Note

    Only use on legal Firrtl. Specifically, the restriction of instance loops must have been checked, or else this pass can infinitely recurse.

  7. case class MPort(name: String, clk: Expression) extends Product with Serializable
  8. case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort]) extends Product with Serializable
  9. trait Pass extends Transform

    Pass is simple transform that is generally part of a larger Transform Has an UnknownForm, because larger Transform should specify form

  10. class PassException extends FirrtlUserException
  11. class PassExceptions extends FirrtlUserException
  12. class RemoveAccesses extends Transform with Pass

    Removes all firrtl.WSubAccess from circuit

  13. case class WidthGeqConstraintAnnotation(loc: ReferenceTarget, exp: ReferenceTarget) extends Annotation with Product with Serializable

Value Members

  1. object CInferMDir extends Transform with Pass
  2. object CInferTypes extends Transform with Pass
  3. object CheckChirrtl extends Transform with Pass with CheckHighFormLike
  4. object CheckFlows extends Transform with Pass
  5. object CheckHighForm extends Transform with Pass with CheckHighFormLike
  6. object CheckInitialization extends Transform with Pass

    Reports errors for any references that are not fully initialized

    Reports errors for any references that are not fully initialized

    Note

    This pass looks for firrtl.WVoids left behind by ExpandWhens

    ,

    Assumes single connection (ie. no last connect semantics)

  7. object CheckTypes extends Transform with Pass
  8. object CheckWidths extends Transform with Pass
  9. object CommonSubexpressionElimination extends Transform with Pass
  10. object ConvertFixedToSInt extends Transform with Pass

    Replaces FixedType with SIntType, and correctly aligns all binary points

  11. object DeadCodeElimination extends Transform
  12. object ExpandConnects extends Transform with Pass
  13. object ExpandWhens extends Transform with Pass

    Expand Whens

    Expand Whens

    This pass does the following things: $ - Remove last connect semantics $ - Remove conditional blocks $ - Eliminate concept of scoping $ - Consolidate attaches

    Note

    Assumes bulk connects and isInvalids have been expanded

    ,

    Assumes all references are declared

  14. object InferTypes extends Transform with Pass
  15. object Legalize extends Transform with Pass
  16. object LowerTypes extends Transform

    Removes all aggregate types from a firrtl.ir.Circuit

    Removes all aggregate types from a firrtl.ir.Circuit

    Example: 

    1. wire foo : { a : UInt<32>, b : UInt<16> }

      lowers to

      wire foo_a : UInt<32>
wire foo_b : UInt<16>
    Note

    Assumes firrtl.ir.SubAccesses have been removed

    ,

    Assumes firrtl.ir.Connects and firrtl.ir.IsInvalids only operate on firrtl.ir.Expressions of ground type

  17. object MemPortUtils
  18. object PadWidths extends Transform with Pass
  19. object PullMuxes extends Transform with Pass
  20. object RemoveAccesses extends Transform with Pass
  21. object RemoveCHIRRTL extends Transform
  22. object RemoveEmpty extends Transform with Pass
  23. object RemoveValidIf extends Transform with Pass

    Remove ValidIf and replace IsInvalid with a connection to zero

  24. object ReplaceAccesses extends Transform with Pass

    Replaces constant firrtl.WSubAccess with firrtl.WSubIndex TODO Fold in to High Firrtl Const Prop

  25. object ResolveFlows extends Transform with Pass
  26. object ResolveKinds extends Transform with Pass
  27. object SplitExpressions extends Transform with Pass
  28. object ToWorkingIR extends Transform with Pass
  29. object Uniquify extends Transform

    Resolve name collisions that would occur in LowerTypes

    Resolve name collisions that would occur in LowerTypes

    Example: 

    1. wire a = { b, c }[2]
wire a_0

      This lowers to:

      wire a__0_b
wire a__0_c
wire a__1_b
wire a__1_c
wire a_0

      There wouldn't be a collision even if we didn't map a -> a_, but there WOULD be collisions in references a[0] and a_0 so we still have to rename a

    Note

    Must be run after InferTypes because ir.DefNodes need type

  30. object VerilogModulusCleanup extends Transform with Pass

    Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog

    Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog

    This pass finds every instance of (a % b) and: 1) adds a temporary node equal to (a % b) with width Max(W(a), W(b)) 2) replaces the reference to (a % b) with a bitslice of the temporary node to get back down to width Min(W(a), W(b))

    This is technically incorrect firrtl, but allows the verilog emitter to emit correct verilog without needing to add temporary nodes

  31. object VerilogPrep extends Transform with Pass

    Makes changes to the Firrtl AST to make Verilog emission easier

    Makes changes to the Firrtl AST to make Verilog emission easier

    - For each instance, adds wires to connect to each port

    • Note that no Namespace is required because Uniquify ensures that there will be no collisions with the lowered names of instance ports - Also removes Attaches where a single Port OR Wire connects to 1 or more instance ports
    • These are expressed in the portCons of WDefInstConnectors
    Note

    The result of this pass is NOT legal Firrtl

  32. object ZeroWidth extends Transform
  33. object createMask
  34. object toBitMask

    Given a mask, return a bitmask corresponding to the desired datatype.

    Given a mask, return a bitmask corresponding to the desired datatype. Requirements:

    • The mask type and datatype must be equivalent, except any ground type in datatype must be matched by a 1-bit wide UIntType.
    • The mask must be a reference, subfield, or subindex The bitmask is a series of concatenations of the single mask bit over the length of the corresponding ground type, e.g.:
    wire mask: {x: UInt<1>, y: UInt<1>}
wire data: {x: UInt<2>, y: SInt<2>}
// this would return:
cat(cat(mask.x, mask.x), cat(mask.y, mask.y))

Deprecated Value Members

  1. object CheckGenders
    Annotations
    @deprecated
    Deprecated

    (Since version 1.2) Use 'CheckFlows'. This object will be removed in 1.3

  2. object ResolveGenders extends Transform with Pass
    Annotations
    @deprecated
    Deprecated

    (Since version 1.2) Use 'ResolveFlows'. This will be removed in 1.3

  3. object VerilogRename extends Transform with Pass
    Annotations
    @deprecated
    Deprecated

    (Since version 1.2) Use transforms.VerilogRename, will be removed in 1.3

Ungrouped