package transforms
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Type Members
- sealed trait BlackBoxHelperAnno extends Annotation
- case class BlackBoxInlineAnno(target: ModuleName, name: String, text: String) extends BlackBoxHelperAnno with SingleTargetAnnotation[ModuleName] with Product with Serializable
-
class
BlackBoxNotFoundException extends FirrtlUserException
Exception indicating that a blackbox wasn't found
- case class BlackBoxPathAnno(target: ModuleName, path: String) extends BlackBoxHelperAnno with SingleTargetAnnotation[ModuleName] with Product with Serializable
- case class BlackBoxResourceAnno(target: ModuleName, resourceId: String) extends BlackBoxHelperAnno with SingleTargetAnnotation[ModuleName] with Product with Serializable
- case class BlackBoxResourceFileNameAnno(resourceFileName: String) extends BlackBoxHelperAnno with NoTargetAnnotation with Product with Serializable
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class
BlackBoxSourceHelper extends Transform
Handle source for Verilog ExtModules (BlackBoxes)
Handle source for Verilog ExtModules (BlackBoxes)
This transform handles the moving of Verilog source for black boxes into the target directory so that it can be accessed by verilator or other backend compilers While parsing it's annotations it looks for a BlackBoxTargetDir annotation that will set the directory where the Verilog will be written. This annotation is typically be set by the execution harness, or directly in the tests
- case class BlackBoxTargetDirAnno(targetDir: String) extends BlackBoxHelperAnno with NoTargetAnnotation with Product with Serializable
-
class
CheckCombLoops extends Transform with RegisteredTransform
Finds and detects combinational logic loops in a circuit, if any exist.
Finds and detects combinational logic loops in a circuit, if any exist. Returns the input circuit with no modifications.
- Exceptions thrown
firrtl.transforms.CheckCombLoops.CombLoopException
if a loop is found- Note
Input form: Low FIRRTL
,Output form: Low FIRRTL (identity transform)
,The pass looks for loops through combinational-read memories
,The pass relies on ExtModulePathAnnotations to find loops through ExtModules
,The pass will throw exceptions on "false paths"
- case class CombinationalPath(sink: ReferenceTarget, sources: Seq[ReferenceTarget]) extends Annotation with Product with Serializable
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class
CombineCats extends Transform
Combine Cat DoPrims
Combine Cat DoPrims
Expands the arguments of any Cat DoPrims if they are references to other Cat DoPrims. Operates only on Cat DoPrims that are node values.
Use MaxCatLenAnnotation to limit the number of elements that can be concatenated. The default maximum number of elements is 10.
- class ConstantPropagation extends Transform with ResolvedAnnotationPaths
-
class
DeadCodeElimination extends Transform with ResolvedAnnotationPaths with RegisteredTransform
Dead Code Elimination (DCE)
Dead Code Elimination (DCE)
Performs DCE by constructing a global dependency graph starting with top-level outputs, external module ports, and simulation constructs as circuit sinks. External modules can optionally be eligible for DCE via the OptimizableExtModuleAnnotation.
Dead code is eliminated across module boundaries. Wires, ports, registers, and memories are all eligible for removal. Components marked with a DontTouchAnnotation will be treated as a circuit sink and thus anything that drives such a marked component will NOT be removed.
This transform preserves deduplication. All instances of a given firrtl.ir.DefModule are treated as the same individual module. Thus, while certain instances may have dead code due to the circumstances of their instantiation in their parent module, they will still not be removed. To remove such modules, use the NoDedupAnnotation to prevent deduplication.
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class
DedupModules extends Transform
Only use on legal Firrtl.
Only use on legal Firrtl.
Specifically, the restriction of instance loops must have been checked, or else this pass can infinitely recurse
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case class
DontTouchAnnotation(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] with Product with Serializable
A component that should be preserved
A component that should be preserved
DCE treats the component as a top-level sink of the circuit
- case class ExtModulePathAnnotation(source: ReferenceTarget, sink: ReferenceTarget) extends Annotation with Product with Serializable
-
class
Flatten extends Transform
Takes flatten annotations for module instances and modules and inline the entire hierarchy of modules down from the annotations.
Takes flatten annotations for module instances and modules and inline the entire hierarchy of modules down from the annotations. This transformation instantiates and is based on the InlineInstances transformation. Note: Inlining a module means inlining all its children module instances
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case class
FlattenAnnotation(target: Named) extends SingleTargetAnnotation[Named] with Product with Serializable
Tags an annotation to be consumed by this transform
-
class
FlattenRegUpdate extends Transform
Flatten register update
Flatten register update
This transform flattens register updates into a single expression on the rhs of connection to the register
-
class
GroupAndDedup extends Transform
Splits a module into multiple modules by grouping its components via GroupAnnotation's Tries to deduplicate the resulting circuit
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case class
GroupAnnotation(components: Seq[ComponentName], newModule: String, newInstance: String, outputSuffix: Option[String] = None, inputSuffix: Option[String] = None) extends Annotation with Product with Serializable
Specifies a group of components, within a module, to pull out into their own module Components that are only connected to a group's components will also be included
Specifies a group of components, within a module, to pull out into their own module Components that are only connected to a group's components will also be included
- components
components in this group
- newModule
suggested name of the new module
- newInstance
suggested name of the instance of the new module
- outputSuffix
suggested suffix of any output ports of the new module
- inputSuffix
suggested suffix of any input ports of the new module
-
class
GroupComponents extends Transform
Splits a module into multiple modules by grouping its components via GroupAnnotation's
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class
IdentityTransform extends Transform
Transform that applies an identity function.
Transform that applies an identity function. This returns an unmodified CircuitState.
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class
InferResets extends Transform
Infers the concrete type of Resets by their connections This is a global inference because ports can be of type Reset
Infers the concrete type of Resets by their connections This is a global inference because ports can be of type Reset
- Note
This transform should be run before DedupModules so that similar Modules from generator languages like Chisel can infer differently
- case class MaxCatLenAnnotation(maxCatLen: Int) extends NoTargetAnnotation with Product with Serializable
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case class
NoDedupAnnotation(target: ModuleName) extends SingleTargetAnnotation[ModuleName] with Product with Serializable
A component, e.g.
A component, e.g. register etc. Must be declared only once under the TopAnnotation
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case class
OptimizableExtModuleAnnotation(target: ModuleName) extends SingleTargetAnnotation[ModuleName] with Product with Serializable
An firrtl.ir.ExtModule that can be optimized
An firrtl.ir.ExtModule that can be optimized
Firrtl does not know the semantics of an external module. This annotation provides some "greybox" information that the external module does not have any side effects. In particular, this means that the external module can be Dead Code Eliminated.
- Note
Unlike DontTouchAnnotation, we don't care if the annotation is deleted
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class
RemoveKeywordCollisions extends Transform
Transform that removes collisions with reserved keywords
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class
RemoveReset extends Transform
Remove Synchronous Reset
Remove Synchronous Reset
- Note
This pass must run after LowerTypes
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class
RemoveWires extends Transform
Replace wires with nodes in a legal, flow-forward order
Replace wires with nodes in a legal, flow-forward order
This pass must run after LowerTypes because Aggregate-type wires have multiple connections that may be impossible to order in a flow-foward way
-
class
RenameModules extends Transform
Rename Modules
Rename Modules
using namespace created by analyses.GetNamespace, create unique names for modules
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class
ReplaceTruncatingArithmetic extends Transform
Replaces non-expanding arithmetic
Replaces non-expanding arithmetic
In the case where the result of
add
orsub
immediately throws away the expanded msb, this transform will replace the operation with a non-expanding operatoraddw
orsubw
respectively.- Note
This replaces some FIRRTL primops with ops that are not actually legal FIRRTL. They are useful for emission to languages that support non-expanding arithmetic (like Verilog)
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class
SimplifyMems extends Transform
Lowers memories without splitting them, but without the complexity of ReplaceMemMacros
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class
VerilogRename extends RemoveKeywordCollisions
Transform that removes collisions with Verilog keywords
Value Members
- object BlackBoxSourceHelper
- object CheckCombLoops
- object CombineCats
- object ConstantPropagation
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object
DedupModules
Utility functions for DedupModules
- object DontCheckCombLoopsAnnotation extends NoTargetAnnotation with Product with Serializable
- object DontTouchAnnotation extends Serializable
- object FlattenRegUpdate
- object InferResets
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object
NoCircuitDedupAnnotation extends NoTargetAnnotation with HasShellOptions with Product with Serializable
If this Annotation exists in an AnnotationSeq, then the firrtl.transforms.DedupModules transform will *NOT* be run on the circuit.
If this Annotation exists in an AnnotationSeq, then the firrtl.transforms.DedupModules transform will *NOT* be run on the circuit.
- set with '--no-dedup'
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object
NoDCEAnnotation extends NoTargetAnnotation with Product with Serializable
Indicate that DCE should not be run
- object ReplaceTruncatingArithmetic
This is the documentation for Firrtl.