dfhdl-compiler-stages
dfhdl-compiler-stages
API
dfhdl
compiler
analysis
stages
verilog
VerilogBackend
VerilogDialect
VerilogPrinter
vhdl
VHDLBackend
VHDLDialect
VHDLPrinter
AddClkRst
BackendCompiler
CompiledDesign
ConnectClkRst
DFHDLUniqueNames
DropBAssignFromSeqProc
DropBinds
DropCondDcls
DropDesignDefs
DropLocalDcls
DropLocalDcls
DropUnreferencedAnons
DropUnreferencedVars
ExplicitClkRstCfg
ExplicitNamedVars
WhenHeader
ExplicitRegInits
ExplicitState
HasDB
HasDB
given_HasDB_DB
NameRegAliases
NameGroup
NamedAliases
Criteria
NamedAnonMultiref
NamedPrev
NamedSelection
Criteria
NamedAnonMultiref
NamedPrev
NamedSelection
OrderMembers
Order
Simple
Order
PrintCodeString
SanityCheck
SimpleOrderMembers
Stage
StageRunner
StageRunner
StagedDesign
StagedDesign
ToED
RegNet
ToRT
UniqueDesigns
VHDLProcToVerilog
ViaConnection
hw
top
options
CompilerOptions
CompilerOptions
backends
verilog
vhdl
dfhdl-compiler-stages
/
dfhdl
/
backends
/
verilog
verilog
dfhdl.backends.verilog
object
verilog
Attributes
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Supertypes
trait
BackendCompiler
class
Object
trait
Matchable
class
Any
Self type
verilog
.
type
Members list
Clear all
Value members
Inherited methods
final
def
compile
[
D
<:
Design
](
sd
:
StagedDesign
[
D
])(
using
co
:
CompilerOptions
,
po
:
PrinterOptions
):
CompiledDesign
[
D
]
Attributes
Inherited from:
BackendCompiler
def
printer
(
designDB
:
DB
)(
using
CompilerOptions
,
PrinterOptions
):
Printer
Attributes
Inherited from:
verilog (hidden)
Concrete fields
val
sv2005
:
verilog
val
sv2012
:
verilog
val
sv2017
:
verilog
val
v2001
:
verilog
Inherited fields
val
dialect
:
VerilogDialect
Attributes
Inherited from:
verilog (hidden)
In this article
Attributes
Members list
Value members
Inherited methods
Concrete fields
Inherited fields