dfhdl.compiler.stages

This stage adds clock and reset ports across the entire design. For each design, clock and reset ports are added once per unique domain configuration.

This connects clock and reset ports across the entire design

This stage converts a derived clock-reset configuration of RT designs/domains to explicit configurations.

This stage propagates initialization values to the reg alias init value, and removes all declaration initializations.

This stage names register aliases (e.g., x.reg) and replaces them with explicit register variables. The most complex mechanism about this stage is the naming conversion convention.

1. If .reg is applied on a named immutable value x or a mutated wire/port that is mutated only once, then that register variable will be named x_reg. If we have several register stages applied, then we create an enumeration. So x.reg(2) yields x_reg1 and x_reg2.
2. If .reg is applied on a named mutable wire x that is mutated more than once, then we treat every new .reg application as a new version of x. In this case we get an enumeration of the version. E.g.:

      val i = DFUInt(8) <> IN
      val o = DFUInt(8) <> OUT
      val x = DFUInt(8) <> VAR
      x := i
      o := x.reg //x_ver1_reg
      x := i + 1
      o := x.reg(2) //x_ver2_reg1, x_ver2_reg2

1. If .reg is applied on an anonymous value, then extrapolate a name suggestion based on the destination variable. This is part of the destination, so it adds _part suffix to the name of the destination. In case of several parts, we create an enumeration. E.g.:

      val i = DFUInt(8) <> IN
      val o = DFUInt(8) <> OUT
      val z = DFUInt(8) <> OUT
      o := (i + 1).reg //o_part_reg
      z := ((i + 1).reg + 7).reg(2) //z_part1_reg, z_part2_reg1, z_part2_reg2

This stage transforms a sequential process from a VHDL style to Verilog style. E.g.,

 process(clk):
   if (clk.rising)
     ....

is transformed into

 process(clk.rising):
   ....