dfhdl-compiler-stages
dfhdl-compiler-stages
API
dfhdl
compiler
analysis
stages
verilog
VerilogBackend
VerilogDialect
VerilogPrinter
vhdl
VHDLBackend
VHDLDialect
VHDLPrinter
AddClkRst
BackendCompiler
CompiledDesign
ConnectClkRst
DFHDLUniqueNames
DropBAssignFromSeqProc
DropBinds
DropCondDcls
DropDesignDefs
DropLocalDcls
DropLocalDcls
DropUnreferencedAnons
DropUnreferencedVars
ExplicitClkRstCfg
ExplicitNamedVars
WhenHeader
ExplicitRegInits
ExplicitState
HasDB
HasDB
given_HasDB_DB
NameRegAliases
NameGroup
NamedAliases
Criteria
NamedAnonMultiref
NamedPrev
NamedSelection
Criteria
NamedAnonMultiref
NamedPrev
NamedSelection
OrderMembers
Order
Simple
Order
PrintCodeString
SanityCheck
SimpleOrderMembers
Stage
StageRunner
StageRunner
StagedDesign
StagedDesign
ToED
RegNet
ToRT
UniqueDesigns
VHDLProcToVerilog
ViaConnection
hw
top
options
CompilerOptions
CompilerOptions
backends
verilog
vhdl
dfhdl-compiler-stages
/
dfhdl
/
dfhdl.compiler
/
dfhdl.compiler.analysis
dfhdl.compiler.analysis
package
dfhdl.compiler.analysis
Members list
Clear all
Extensions
Extensions
extension
(
designDB
:
DB
)
def
getOpenOutPorts
:
List
[
DFVal
]
def
getUnusedBitsValues
:
List
[(
DFVal
,
Int
,
Int
)]
def
getUnusedTaggedValues
:
List
[
DFVal
]
In this article
Members list
Extensions
Extensions