dfhdl-compiler-stages
dfhdl-compiler-stages
API
dfhdl
compiler
analysis
stages
verilog
VerilogBackend
VerilogDialect
VerilogPrinter
vhdl
DclScope
VHDLBackend
VHDLDialect
VHDLPrinter
AddClkRst
AddMagnets
BackendCompiler
CompiledDesign
ConnectMagnets
DFHDLUniqueNames
DropBAssignFromSeqProc
DropBinds
DropCondDcls
DropDesignDefs
DropLocalDcls
DropLocalDcls
DropMagnets
DropOpaques
DropOpaquesAll
DropUnreferencedAnons
DropUnreferencedVars
ExplicitClkRstCfg
ExplicitNamedVars
WhenHeader
ExplicitRegInits
ExplicitState
HasDB
HasDB
given_HasDB_DB
NameRegAliases
NameGroup
NamedAliases
Criteria
NamedAnonMultiref
NamedPrev
NamedSelection
Criteria
NamedAnonMultiref
NamedPrev
NamedSelection
OrderMembers
Order
Simple
Order
PrintCodeString
SanityCheck
SimpleOrderMembers
Stage
StageRunner
StageRunner
StagedDesign
StagedDesign
ToED
RegNet
ToRT
UniqueDesigns
VHDLProcToVerilog
ViaConnection
options
CompilerOptions
CompilerOptions
Backend
CommitFolder
LogLevel
NewFolderForTop
PrintDesignCodeAfter
PrintDesignCodeBefore
PrintGenFiles
backends
verilog
vhdl
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