dfhdl-compiler-stages
dfhdl-compiler-stages
API
dfhdl
compiler
analysis
stages
verilog
VerilogBackend
VerilogDialect
VerilogPrinter
vhdl
DclScope
VHDLBackend
VHDLDialect
VHDLPrinter
AddClkRst
AddMagnets
BackendCompiler
CompiledDesign
ConnectMagnets
DFHDLUniqueNames
DropBAssignFromSeqProc
DropBinds
DropCondDcls
DropDesignDefs
DropLocalDcls
DropLocalDcls
DropMagnets
DropOpaques
DropOpaquesAll
DropUnreferencedAnons
DropUnreferencedVars
ExplicitClkRstCfg
ExplicitNamedVars
WhenHeader
ExplicitRegInits
ExplicitState
HasDB
HasDB
given_HasDB_DB
NameRegAliases
NameGroup
NamedAliases
Criteria
NamedAnonMultiref
NamedPrev
NamedSelection
Criteria
NamedAnonMultiref
NamedPrev
NamedSelection
OrderMembers
Order
Simple
Order
PrintCodeString
SanityCheck
SimpleOrderMembers
Stage
StageRunner
StageRunner
StagedDesign
StagedDesign
ToED
RegNet
ToRT
UniqueDesigns
VHDLProcToVerilog
ViaConnection
options
CompilerOptions
CompilerOptions
Backend
CommitFolder
LogLevel
NewFolderForTop
PrintDesignCodeAfter
PrintDesignCodeBefore
PrintGenFiles
backends
verilog
vhdl
dfhdl-compiler-stages
/
dfhdl
/
dfhdl.options
/
CompilerOptions
/
Backend
Backend
dfhdl.options.CompilerOptions.Backend
object
Backend
Attributes
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class
Object
trait
Matchable
class
Any
Self type
Backend
.
type
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Givens
Givens
given
given_Backend
:
Backend
given
given_Conversion_BackendCompiler_Backend
:
Conversion
[
BackendCompiler
,
Backend
]
Exports
Defined exports
final
val
verilog
:
verilog
Exported from
backends
final
type
verilog
=
verilog
Exported from
backends$
final
val
vhdl
:
vhdl
Exported from
backends
final
type
vhdl
=
vhdl
Exported from
backends$
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Givens
Exports
Defined exports