class Apb2Net extends Module
APB2 Network
Parameterizable number of initiators and memory mapped targets. Arbitration between initiators for access to targets. Default parameterization connects one APB initiator to two APB targets. Cross-bar network topology. To be clear, this Module drives its targets and responds to its initiators, but where it is instantiated its initators are targets and its targets are initiators.
- To do
implement PIPE_CTRL as described
- Note
targets are assumed to be contiguously mapped from the base (with no gaps in map, i.e. if there are two targets of size 4kB and 8kB, respectively, and the base address of the first is @0x0 then the base address of the second is implicitly @4kB)
,this module is not optimized for throughput, but for easy timing closure and low power
Linear Supertypes
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- Apb2Net
- Module
- ImplicitReset
- ImplicitClock
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Instance Constructors
- new Apb2Net(BASE_ADDR: Int = 0, GRANULE_SIZE_K: Int = 4, NUM_INIT: Int = 1, NUM_TARG: Int = 2, TARGET_SIZES: Array[Int] = new Array[Int](2), DATA_W: Int = 32, ADDR_W: Int = 32, PIPE_CTRL: Int = 0)
- BASE_ADDR
base address of the network in bytes (must be multiple of GRANULE_SIZE_K)
- GRANULE_SIZE_K
minimum size of address space of one APB target (kB >= 4)
- NUM_INIT
number of initiators
- NUM_TARG
number of targets
- TARGET_SIZES
array of target sizes (multiples of GRANULE_SIZE_K)
- DATA_W
the width of the APB data buses in bits
- ADDR_W
the width of the APB address buses in bits
- PIPE_CTRL
adds pipeline register stages as follows 0: none, 1: after arbitration, 2: for each target
Value Members
- final def !=(arg0: Any): Boolean
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- final def ##: Int
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- val ADDR_W: Int
- val APB_ALGN: Int
- val ArbInst: Arbiter[Apb2ReqCtrl]
- val BASE_ADDR: Int
- val DATA_W: Int
- val GRANULE_SIZE_K: Int
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
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- BaseModule
- val NUM_BYTE: Int
- val NUM_INIT: Int
- val NUM_TARG: Int
- val PIPE_CTRL: Int
- val SEL_ALGN: Int
- val TARGET_SIZES: Array[Int]
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
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- val activeReq: Bool
- val apb2Choice: DecoupledIO[Apb2ReqCtrl]
- val apb2ChoiceRsp: Apb2Rsp
- val apb2InitChoiceReqFF: Apb2Req
- val apb2ReqVec: Vec[DecoupledIO[Apb2ReqCtrl]]
- val apb2TargetSel: UInt
- val apb2TargetSelRspFF: Apb2Rsp
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- def implicitReset: Reset
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- def portsSize: Int
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- val reqVec: Vec[Bool]
- final val reset: Reset
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- Module
- def resetType: Type
- Definition Classes
- Module
- val stateFF: Apb2NetStateEnum.Type
- def suggestName(seed: => String): Apb2Net.this.type
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- object Apb2NetStateEnum extends ChiselEnum
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(Since version 9)
- def override_clock: Option[Clock]
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(Since version Chisel 3.5) Use withClock at Module instantiation
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(Since version Chisel 3.5) Use withClock at Module instantiation
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(Since version Chisel 3.5) Use withClock at Module instantiation
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(Since version Chisel 3.5) Use withClock at Module instantiation