p

ambel

package ambel

Ordering
  1. Alphabetic
Visibility
  1. Public
  2. Protected

Type Members

  1. abstract class AmbaUnitTester extends AnyFlatSpec with BaseUnitTester

    AMBA Unit Tester Base Class

    To do

    use NUM_NIBBLE to format addr/data strings

  2. abstract class Apb2Bundle extends Bundle
  3. class Apb2CSTrgt extends Module

    AMBA APB2 protocol Control/Status register target (slave) generator

    Apb2CSTrgt

    AMBA APB2 protocol Control/Status register target (slave) generator

    To do

    implement pProt

  4. class Apb2IO extends Apb2Bundle
  5. class Apb2Net extends Module

    Parameterizable number of initiators and memory mapped targets.

    APB2 Network

    Parameterizable number of initiators and memory mapped targets. Arbitration between initiators for access to targets. Default parameterization connects one APB initiator to two APB targets. Cross-bar network topology. To be clear, this Module drives its targets and responds to its initiators, but where it is instantiated its initators are targets and its targets are initiators.

    To do

    implement PIPE_CTRL as described

    Note

    targets are assumed to be contiguously mapped from the base (with no gaps in map, i.e. if there are two targets of size 4kB and 8kB, respectively, and the base address of the first is @0x0 then the base address of the second is implicitly @4kB)

    ,

    this module is not optimized for throughput, but for easy timing closure and low power

  6. class Apb2RegFile extends Module

    APB2 target implementing bank of 4x 32 bit (by default) read/write registers

    Apb2RegFile

    APB2 target implementing bank of 4x 32 bit (by default) read/write registers

  7. class Apb2Req extends Apb2Bundle

    Direction of AMBA APB2 IOs are from target perspective (i.e.

    AMBA APB2 IO Bundle

    Direction of AMBA APB2 IOs are from target perspective (i.e. request = Input, response = Output)

  8. class Apb2ReqCtrl extends Apb2Bundle

    Apb2ReqCtrl is the same as Apb2Req Bundle but without pSel.

    Apb2ReqCtrl Bundle

    Apb2ReqCtrl is the same as Apb2Req Bundle but without pSel. This Bundle is used below in DecoupledIO where the pSel signal from Apb2Req Bundle is used to drive valid.

  9. class Apb2Rsp extends Apb2Bundle
  10. class Apb2Slice extends Module

    APB2 bus register slice for pipelining/timing closure.

    APB2 Slice

    APB2 bus register slice for pipelining/timing closure.

  11. case class BitField(bits: List[Int], name: String, mode: Option[String] = None, resetVal: Option[Int] = None, comment: Option[String] = None) extends Product with Serializable

    BitField

  12. case class BitFieldDetails(reg: UInt, pos: Int, width: Int, mode: String, name: String) extends Product with Serializable

    class holding the actual bits (i.e.

    BitFieldDetails

    class holding the actual bits (i.e. hardware) for a single bitfield of a register along with its position, width, mode and name

  13. class ExampleApb2T extends Module

    (REG_DESC_JSON="src/main/json/Example.json") Uses Bundles above on IO and makes ordered connection to MixedVec IO on Apb2CSTrgt instance

    Wrapper Module for Apb2CSTrgt

    (REG_DESC_JSON="src/main/json/Example.json") Uses Bundles above on IO and makes ordered connection to MixedVec IO on Apb2CSTrgt instance

    THIS IS AUTO-GENERATED CODE - DO NOT MODIFY BY HAND!

  14. class GenCSTrgt extends Module

    Generic (bus protocol agnostic) Control/Status register target generator

    GenCSTrgt

    Generic (bus protocol agnostic) Control/Status register target generator

  15. case class Register(offset: Int, name: String, typeRef: String, comment: Option[String] = None) extends Product with Serializable

    Register

  16. case class RegisterAttr(offset: Int, width: Int, typeRef: String) extends Product with Serializable

    RegisterAttr

  17. class RegisterBitLists extends AnyRef

    ListMaps of RW, RO, WO and WC register bits suitable for generation of Control/Status register target IOs

    RegisterBitLists

    ListMaps of RW, RO, WO and WC register bits suitable for generation of Control/Status register target IOs

  18. case class RegisterBits(name: String, fields: List[BitField]) extends Product with Serializable

    Register attributes: Name and BitField List

    RegisterAttr

    Register attributes: Name and BitField List

  19. case class RegisterDesc(regMap: List[Register], regTypes: List[RegisterType]) extends Product with Serializable

    Register description: Register map List and register type List

    RegisterDesc

    Register description: Register map List and register type List

  20. class RegisterDescDecoder extends AnyRef
  21. class RegisterElements extends AnyRef

    Lists of separated register description elements ultimately used to build an array of registers suitable for hardware generation

    RegisterElements

    Lists of separated register description elements ultimately used to build an array of registers suitable for hardware generation

    To do

    implement check that there are no spaces in register or regType names in JSON

  22. case class RegisterType(typeRef: String, width: Int, fields: List[BitField], comment: Option[String] = None) extends Product with Serializable

    Register type: type reference string, register width in bits and List of BitFields, optional description comment

    RegisterType

    Register type: type reference string, register width in bits and List of BitFields, optional description comment

  23. class SimpleApb2T extends Module

    (REG_DESC_JSON="src/main/json/Simple.json") Uses Bundles above on IO and makes ordered connection to MixedVec IO on Apb2CSTrgt instance

    Wrapper Module for Apb2CSTrgt

    (REG_DESC_JSON="src/main/json/Simple.json") Uses Bundles above on IO and makes ordered connection to MixedVec IO on Apb2CSTrgt instance

    THIS IS AUTO-GENERATED CODE - DO NOT MODIFY BY HAND!

  24. class _ExampleApb2TRoVec_ extends Bundle
  25. class _ExampleApb2TRwVec_ extends Bundle

    (REG_DESC_JSON="src/main/json/Example.json")

    Bundles for Connection to Apb2CSTrgt

    (REG_DESC_JSON="src/main/json/Example.json")

    THIS IS AUTO-GENERATED CODE - DO NOT MODIFY BY HAND!

  26. class _ExampleApb2TWcVec_ extends Bundle
  27. class _ExampleApb2TWoVec_ extends Bundle
  28. class _SimpleApb2TRoVec_ extends Bundle
  29. class _SimpleApb2TRwVec_ extends Bundle

    (REG_DESC_JSON="src/main/json/Simple.json")

    Bundles for Connection to Apb2CSTrgt

    (REG_DESC_JSON="src/main/json/Simple.json")

    THIS IS AUTO-GENERATED CODE - DO NOT MODIFY BY HAND!

  30. class _SimpleApb2TWoVec_ extends Bundle

Value Members

  1. object Apb2CSTrgtDriver extends App

    Run this driver as follows...

    Verilog generation boiler plate

    Run this driver as follows... From within sbt use:

    runMain ambel.Apb2CSTrgtDriver --target-dir src/main/verilog --log-level info --log-file Apb2CSTrgtDriver.log
  2. object Apb2NetDriver extends App

    Run this driver as follows...

    Verilog generation boiler plate

    Run this driver as follows... From within sbt use:

    runMain ambel.Apb2NetDriver --target-dir src/main/verilog --log-level info --log-file Apb2NetDriver.log
  3. object Apb2RegFileDriver extends App

    Run this driver as follows...

    Verilog generation boiler plate

    Run this driver as follows... From within sbt use:

    runMain ambel.Apb2RegFileDriver --target-dir src/main/verilog --log-level info --log-file Apb2RegFileDriver.log
  4. object Apb2SliceDriver extends App

    Run this driver as follows...

    Verilog generation boiler plate

    Run this driver as follows... From within sbt use:

    runMain ambel.Apb2SliceDriver --target-dir src/main/verilog --log-level info --log-file Apb2SliceDriver.log
  5. object ExampleApb2TDriver extends App
  6. object SimpleApb2TDriver extends App

Ungrouped