class GenCSTrgt extends Module
GenCSTrgt
Generic (bus protocol agnostic) Control/Status register target generator
Linear Supertypes
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Inherited
- GenCSTrgt
- Module
- ImplicitReset
- ImplicitClock
- RawModule
- BaseModule
- IsInstantiable
- HasId
- InstanceId
- AnyRef
- Any
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Visibility
- Public
- Protected
Instance Constructors
- new GenCSTrgt(ADDR_W: Int, DATA_W: Int, REG_DESC_JSON: String = "", GEN_MODULE: Boolean = false, VERBOSE: Boolean = false)
- ADDR_W
the width of the address bus in bits
- DATA_W
the width of the data bus in bits
- REG_DESC_JSON
the path to the register description JSON file
- GEN_MODULE
enables generation of a wrapper Module which uses generated Bundles suitable for connection to the generated MixedVec IOs. The signal names used in the Bundles match their corresponding register and bit field names, as specified in the JSON. They are declared in the same order as the entries of the corresponding MixedVec and connected in order
- VERBOSE
enables verbose output during generation
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- val INDEX_W: Int
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
- Attributes
- protected
- Definition Classes
- BaseModule
- val NUM_BITS_SHIFT: Int
- val NUM_BYTE: Int
- val NUM_REGS: Int
- val REQD_W: Int
- val RegDescDecoder: RegisterDescDecoder
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _moduleDefinitionIdentifierProposal: String
- Attributes
- protected
- Definition Classes
- BaseModule
- def _sourceInfo: SourceInfo
- Attributes
- protected
- Definition Classes
- BaseModule
- def _traitModuleDefinitionIdentifierProposal: Option[String]
- Attributes
- protected
- Definition Classes
- BaseModule
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def atModuleBodyEnd(gen: => Unit): Unit
- Attributes
- protected
- Definition Classes
- RawModule
- val bundlePrefix: String
- val chisel3ModuleFileName: String
- val chisel3ModuleFilePath: String
- val chisel3ModuleName: String
- def circuitName: String
- Definition Classes
- HasId
- final val clock: Clock
- Definition Classes
- Module
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
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- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @HotSpotIntrinsicCandidate() @native()
- final val definitionIdentifier: String
- Definition Classes
- BaseModule
- def desiredName: String
- Definition Classes
- BaseModule
- def endIOCreation()(implicit si: SourceInfo): Unit
- Definition Classes
- BaseModule
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @HotSpotIntrinsicCandidate() @native()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def implicitClock: Clock
- Attributes
- protected
- Definition Classes
- Module → ImplicitClock
- def implicitReset: Reset
- Attributes
- protected
- Definition Classes
- Module → ImplicitReset
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- val io: Bundle { ... /* 11 definitions in type refinement */ }
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val jsonString: String
- final lazy val name: String
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @HotSpotIntrinsicCandidate() @native()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @HotSpotIntrinsicCandidate() @native()
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- val readDataFF: UInt
- val readErrorFF: Bool
- val regAlias: Bool
- val regBits: RegisterBitLists
- val regDesc: Option[RegisterDesc]
- val regElements: RegisterElements
- val regIndex: UInt
- final val reset: Reset
- Definition Classes
- Module
- def resetType: Type
- Definition Classes
- Module
- val roBundleBuffer: ListBuffer[String]
- val roConnectBuffer: ListBuffer[String]
- var roIdx: Int
- val roIt: Iterator[UInt]
- val rwBundleBuffer: ListBuffer[String]
- val rwConnectBuffer: ListBuffer[String]
- var rwIdx: Int
- val rwIt: Iterator[UInt]
- def suggestName(seed: => String): GenCSTrgt.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- final def toRelativeTarget(root: Option[BaseModule]): IsModule
- Definition Classes
- BaseModule
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- val wcBundleBuffer: ListBuffer[String]
- val wcConnectBuffer: ListBuffer[String]
- var wcIdx: Int
- val wcIt: Iterator[UInt]
- val woBundleBuffer: ListBuffer[String]
- val woConnectBuffer: ListBuffer[String]
- var woIdx: Int
- val woIt: Iterator[UInt]
- def writeBundleConnect(f: BitFieldDetails, index: Int): String
- def writeBundleMember(f: BitFieldDetails): String
- val writeErrorFF: Bool
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
(Since version 9)
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation