class SInt extends BitVector with Num[SInt] with MinMaxProvider with DataPrimitives[SInt] with BaseTypePrimitives[SInt] with BitwiseOp[SInt]
The SInt type corresponds to a vector of bits that can be used for signed integer arithmetic.
val mySInt = SInt(8 bits) mySInt := S(4, 8 bits) + S"0000_1111" mySInt := S(4) - S"h1A"
- See also
- Alphabetic
- By Inheritance
- SInt
- BitwiseOp
- BaseTypePrimitives
- DataPrimitives
- MinMaxProvider
- Num
- BitVector
- Widthable
- WidthProvider
- BaseType
- Expression
- StatementDoubleLinkedContainer
- DoubleLinkedContainer
- DeclarationStatement
- LeafStatement
- Statement
- BaseNode
- ExpressionContainer
- Data
- InComponent
- OverridedEqualsHashCode
- SpinalTagReady
- Assignable
- NameableByComponent
- Nameable
- OwnableRef
- ContextUser
- ScalaLocated
- GlobalDataUser
- AnyRef
- Any
- Hide All
- Show All
- Public
- Protected
Instance Constructors
- new SInt()
Type Members
- abstract type RefOwnerType
- Definition Classes
- OwnableRef
- type T = SInt
Used to know the data type of the children class of BitVector
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def ##(right: Data): Bits
Concatenation between two signals
Concatenation between two signals
- Definition Classes
- Data
- final def ##: Int
- Definition Classes
- AnyRef → Any
- def #*(count: Int): Bits
- Definition Classes
- Data
- def %(right: SInt): SInt
Hardware modulo
- def &(right: SInt): SInt
Bitwise AND operator
- def *(right: SInt): SInt
Hardware multiplication
- def +(right: SInt): SInt
Hardware addition
- def +^(right: SInt): SInt
Hardware safe addition with 1 bit expand
- def +|(right: SInt): SInt
Hardware safe addition with saturation
- def -(right: SInt): SInt
Hardware subtraction
- def -^(right: SInt): SInt
Hardware safe subtraction with 1 bit expand
- def -|(right: SInt): SInt
Hardware safe subtraction with saturation
- def /(right: SInt): SInt
Hardware division
- def :=(value: String): Unit
- def :=(rangesValue: (Any, Any), _rangesValues: (Any, Any)*): Unit
Assign a range value to a SInt
Assign a range value to a SInt
- rangesValue
The first range value
- _rangesValues
Others range values
core.io.interrupt = (0 -> uartCtrl.io.interrupt, 1 -> timerCtrl.io.interrupt, default -> false)
Example: - def :=(that: SInt)(implicit loc: Location): Unit
Standard hardware assignment, equivalent to
<=in VHDL/VerilogStandard hardware assignment, equivalent to
<=in VHDL/Verilog- Definition Classes
- DataPrimitives
- def <(right: SInt): Bool
Hardware "is less than right"
- def <<(that: UInt): SInt
Logical shift Left (output width will increase of : w(this) + max(that) bits
- def <<(that: Int): SInt
Hardware arithmetic left shift (
w(T) = w(this) + shift) - def <=(right: SInt): Bool
Hardware "is equal or less than right"
- def <>(that: SInt)(implicit loc: Location): Unit
Automatic connection between two hardware signals or two bundles of the same type.
Automatic connection between two hardware signals or two bundles of the same type.
Direction is inferred by using signal direction (
in/out). (Similar behavior to:=)- Definition Classes
- DataPrimitives
- def =/=(that: SInt): Bool
isNotEqualTocomparison between two SpinalHDL dataisNotEqualTocomparison between two SpinalHDL data- Definition Classes
- DataPrimitives
- def =/=(that: MaskedLiteral): Bool
BitVector is not equal to MaskedLiteral
BitVector is not equal to MaskedLiteral
- Definition Classes
- BitVector
- def =::=(that: SInt): Bool
- Definition Classes
- DataPrimitives
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def ===(that: SInt): Bool
isEqualTocomparison between two SpinalHDL dataisEqualTocomparison between two SpinalHDL data- Definition Classes
- DataPrimitives
- def ===(that: MaskedLiteral): Bool
Compare a BitVector with a MaskedLiteral (M"110--0")
Compare a BitVector with a MaskedLiteral (M"110--0")
- that
the maskedLiteral
- returns
a Bool data containing the result of the comparison
- Definition Classes
- BitVector
val myBool = myBits === M"0-1"
Example: - def >(right: SInt): Bool
Hardware "is greater than right"
- def >=(right: SInt): Bool
Hardware "is equal or greater than right"
- def >>(that: UInt): SInt
Logical shift Right (output width == input width)
- def >>(that: Int): SInt
Hardware arithmetic right shift (
w(T) = w(this) - shift) - def @*(count: Int): SInt
- def @@(that: Bool): SInt
Concatenation between a
SIntand aBool - def @@(that: UInt): SInt
Concatenation between a
SIntandUInt - def @@(that: SInt): SInt
Concatenation between two
SIntConcatenation between two
SInt- that
an SInt to append
- returns
a new
SIntof width (width(this) + width(right))
val mySInt = sInt1 @@ sInt2
Example: - def IFparent: Data
- Definition Classes
- Data
- def Q: QFormat
- Definition Classes
- Num
- def \(that: SInt): SInt
Use as
\=to have the same behavioral as VHDL variableUse as
\=to have the same behavioral as VHDL variable- Definition Classes
- DataPrimitives
- def ^(right: SInt): SInt
Bitwise XOR operator
- def _fixEntry(roundN: Int, roundType: RoundType, satN: Int): SInt
- Attributes
- protected
- val _spinalTags: LinkedHashSet[SpinalTag]
- Definition Classes
- SpinalTagReady
- def addAttribute(attribute: Attribute): SInt.this.type
- Definition Classes
- BaseType → Data → SpinalTagReady
- def addAttribute(name: String, value: Int): SInt.this.type
- Definition Classes
- SpinalTagReady
- def addAttribute(name: String, value: String): SInt.this.type
- Definition Classes
- SpinalTagReady
- def addAttribute(name: String): SInt.this.type
- Definition Classes
- SpinalTagReady
- def addTag[T <: SpinalTag](spinalTag: T): SInt.this.type
- Definition Classes
- SpinalTagReady
- def addTags(h: SpinalTag, tail: SpinalTag*): SInt.this.type
- Definition Classes
- SpinalTagReady
- def addTags[T <: SpinalTag](tags: Iterable[T]): SInt.this.type
- Definition Classes
- SpinalTagReady
- val algoIncrementale: Int
- Definition Classes
- BaseNode
- val algoInt: Int
- Definition Classes
- BaseNode
- def allowDirectionLessIo(): SInt.this.type
Allow a signal of an io
Bundleto be directionless.Allow a signal of an io
Bundleto be directionless.- Definition Classes
- Data
- See also
- def allowOverride(): SInt.this.type
Allow a signal to be overridden.
Allow a signal to be overridden.
- Definition Classes
- Data
- See also
- def allowPartialyAssigned(): SInt.this.type
Allow a register to be partially assigned
Allow a register to be partially assigned
- Definition Classes
- Data
- def allowPruning(): SInt.this.type
- Definition Classes
- Data
- def allowSimplifyIt(): SInt.this.type
- def allowUnsetRegToAvoidLatch(): SInt.this.type
Allow a register to have only an init (no assignments)
Allow a register to have only an init (no assignments)
- Definition Classes
- Data
- See also
- def andMask(that: Bool): SInt.this.type
- Definition Classes
- BitVector
- def andR: Bool
Hardware logical AND of all bits
Hardware logical AND of all bits
Equivalent to
this.asBits === ((BigInt(1) << getWidth) - 1).- Definition Classes
- BitVector
- def apply(offset: UInt, bitCount: BitCount): SInt.this.type
Return a range of bits at offset and of width bitCount
- def apply(offset: Int, bitCount: BitCount): SInt.this.type
Return a range of bits at offset and of width bitCount
- def apply(bitId: UInt): Bool
Return the bit at index bitId
- def apply(bitId: Int): Bool
Return the bit at index bitId
- def apply(range: Range): SInt.this.type
Return a range of bits
Return a range of bits
- Definition Classes
- BitVector
val myBool = myBits(3 downto 1)
Example: - def as[T <: Data](dataType: HardType[T]): T
- Definition Classes
- Data
- def asBits: Bits
Cast signal to Bits
- def asBool: Bool
Return
this.lsbReturn
this.lsb- Definition Classes
- BitVector
- def asBools: Vec[Bool]
Cast the
BitVectorinto a vector ofBoolCast the
BitVectorinto a vector ofBool- Definition Classes
- BitVector
- def asData: Data
- Definition Classes
- Data
- def asInOut(): SInt.this.type
Set a signal as
inout - def asInput(): SInt.this.type
Set a data as input
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def asOutput(): SInt.this.type
Set a data as output
- def asUInt: UInt
Cast a SInt into an UInt
Cast a SInt into an UInt
- returns
a UInt data
myUInt := mySInt.asUInt
Example: - def assignDontCare(): SInt.this.type
- def assignDontCareToUnasigned(): SInt.this.type
- Definition Classes
- Data
- def assignFormalRandom(kind: RandomExpKind): Unit
- final def assignFrom(that: AnyRef, target: AnyRef = this)(implicit loc: Location): Unit
- Definition Classes
- Data
- def assignFromBits(bits: Bits, hi: Int, lo: Int): Unit
- def assignFromBits(bits: Bits): Unit
- def assignFromBits(bits: Bits, offset: Int, bitCount: BitCount): Unit
- Definition Classes
- Data
- def assignFromImpl(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit
- Attributes
- protected
- Definition Classes
- BaseType → Assignable
- def bitsRange: Range
- Definition Classes
- BitVector
- def ceil(n: Int, align: Boolean = true): SInt
SIntceil - def ceil(width: BitCount, align: Boolean): SInt
lowest n bits Round Operation by BitCount
lowest n bits Round Operation by BitCount
- Definition Classes
- Num
- def ceilToInf(n: Int, align: Boolean = true): SInt
SInt roundUp lowest m bits, friendly for hardware timing and area sign * ceil(abs(x))
- def ceilToInf(width: BitCount, align: Boolean): SInt
- Definition Classes
- Num
- def cldCount: Int
- Definition Classes
- DoubleLinkedContainer
- def clearAll(): SInt.this.type
Clear all bits
- var clockDomain: ClockDomain
- Definition Classes
- BaseType
- def clone(): SInt.this.type
- def component: Component
- Definition Classes
- ContextUser
- final def compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit
- Definition Classes
- Assignable
- val compositeAssign: Assignable
- Definition Classes
- Assignable
- def copyDirectionOf(that: SInt): Unit
- Definition Classes
- DataPrimitives
- def copyDirectionOfImpl(that: Data): SInt.this.type
- def default(that: => SInt): SInt
Set a default value to a signal.
Set a default value to a signal.
- Definition Classes
- DataPrimitives
- See also
- def dirString(): String
- Definition Classes
- Data
- def dlcAppend(that: AssignmentStatement): SInt.this.type
- Definition Classes
- DoubleLinkedContainer
- def dlcForeach[T >: AssignmentStatement](func: (T) => Unit): Unit
- Definition Classes
- DoubleLinkedContainer
- def dlcHasOnlyOne: Boolean
- Definition Classes
- DoubleLinkedContainer
- val dlcHead: AssignmentStatement
- Definition Classes
- DoubleLinkedContainer
- def dlcIsEmpty: Boolean
- Definition Classes
- DoubleLinkedContainer
- val dlcLast: AssignmentStatement
- Definition Classes
- DoubleLinkedContainer
- def dlcPrepend(that: AssignmentStatement): SInt.this.type
- Definition Classes
- DoubleLinkedContainer
- def dontSimplifyIt(): SInt.this.type
- def drop(n: Int): Bits
Drop lowest n bits
Drop lowest n bits
- returns
data10bits(9 downto 4)
- Definition Classes
- BitVector
val res = data10bits.drop(4)
Example: - def dropHigh(n: Int): Bits
Drop highest n bits
Drop highest n bits
- returns
data10bits(5 downto 0)
- Definition Classes
- BitVector
val res = data10bits.dropHigh(4)
Example: - def dropLow(n: Int): Bits
- Definition Classes
- BitVector
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(obj: Any): Boolean
- Definition Classes
- OverridedEqualsHashCode → AnyRef → Any
- def existsTag(cond: (SpinalTag) => Boolean): Boolean
- Definition Classes
- SpinalTagReady
- def expand: SInt
- def filterTag(cond: (SpinalTag) => Boolean): Iterable[SpinalTag]
- Definition Classes
- SpinalTagReady
- def findTag(cond: (SpinalTag) => Boolean): Option[SpinalTag]
- Definition Classes
- SpinalTagReady
- def fixTo(q: QFormat): SInt
- def fixTo(q: QFormat, roundType: RoundType): SInt
- def fixTo(q: QFormat, roundType: RoundType, sym: Boolean): SInt
- def fixTo(section: Inclusive): SInt
- def fixTo(section: Inclusive, roundType: RoundType): SInt
- def fixTo(section: Inclusive, roundType: RoundType, sym: Boolean): SInt
- def flatten: Seq[BaseType]
- def flattenForeach(body: (BaseType) => Unit): Unit
- def flattenLocalName: Seq[String]
- def flip(): SInt.this.type
Flip the direction of the signal.
Flip the direction of the signal.
inandoutare swapped,inoutstay the same.- Definition Classes
- Data
- def floor(n: Int): SInt
return
w(this)-nbits - def floor(width: BitCount): SInt
- Definition Classes
- Num
- def floorToZero(n: Int): SInt
SInt roundUp lowest m bits, friendly for hardware timing and area sign * floor(abs(x))
- def floorToZero(width: BitCount): SInt
- Definition Classes
- Num
- def foreachClockDomain(func: (ClockDomain) => Unit): Unit
- def foreachDrivingExpression(func: (Expression) => Unit): Unit
- Definition Classes
- ExpressionContainer
- def foreachExpression(func: (Expression) => Unit): Unit
- Definition Classes
- DeclarationStatement → ExpressionContainer
- def foreachReflectableNameables(doThat: (Any) => Unit): Unit
- Definition Classes
- Nameable
- def foreachStatements(func: (AssignmentStatement) => Unit): Unit
- Definition Classes
- StatementDoubleLinkedContainer
- def foreachTag(body: (SpinalTag) => Unit): Unit
- Definition Classes
- SpinalTagReady
- def freeze(): SInt.this.type
- def getAheadValue(): SInt.this.type
For a register, get the value it will have at the next clock, as a combinational signal.
- def getAllTrue: SInt.this.type
- def getBitsWidth: Int
Return the width of the data
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @HotSpotIntrinsicCandidate() @native()
- def getComponent(): Component
- Definition Classes
- Data → InComponent → NameableByComponent
- def getComponents(): Seq[Component]
Get current component with all parents
Get current component with all parents
- Definition Classes
- InComponent
- def getDirection: IODirection
- Definition Classes
- Data
- def getDisplayName(): String
- Definition Classes
- Nameable
- def getDrivingReg(reportError: Boolean = true): SInt.this.type
- Definition Classes
- BaseType
- def getInstanceCounter: Int
- Definition Classes
- ContextUser
- def getMode: Byte
- Attributes
- protected
- Definition Classes
- Nameable
- def getMuxType[T <: Data](list: TraversableOnce[T]): HardType[T]
- def getName(default: String): String
- Definition Classes
- NameableByComponent → Nameable
- def getName(): String
- Definition Classes
- NameableByComponent → Nameable
- def getPartialName(): String
- Definition Classes
- Nameable
- def getPath(from: Component, to: Component): Seq[Component]
- Definition Classes
- NameableByComponent
- def getRealSource: Any
- Definition Classes
- Assignable
- def getRealSourceNoRec: Any
- Definition Classes
- Data → Assignable
- def getRefOwnersChain(): List[Any]
- Definition Classes
- OwnableRef
- def getRootParent: Data
- Definition Classes
- Data
- def getRtlPath(separator: String = "/"): String
- Definition Classes
- Data
- def getScalaLocationLong: String
- Definition Classes
- ScalaLocated
- def getScalaLocationShort: String
- Definition Classes
- ScalaLocated
- def getScalaTrace(): Throwable
- Definition Classes
- ScalaLocated
- def getSingleDriver: Option[SInt.this.type]
- Definition Classes
- BaseType
- def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]
- Definition Classes
- SpinalTagReady
- def getTags(): LinkedHashSet[SpinalTag]
- Definition Classes
- SpinalTagReady
- def getTypeObject: TypeSInt
- Definition Classes
- SInt → Expression
- def getWidth: Int
- Definition Classes
- Widthable → WidthProvider
- def getWidthNoInferation: Int
Return the width
Return the width
- Definition Classes
- BitVector
- def getWidthStringNoInferation: String
- Definition Classes
- BitVector
- def getZero: SInt.this.type
Create a signal set to 0
- def getZeroUnconstrained: SInt.this.type
- val globalData: GlobalData
- Definition Classes
- GlobalDataUser
- def hasAssignement: Boolean
- Definition Classes
- BaseType
- def hasDataAssignment: Boolean
- Definition Classes
- BaseType
- def hasInit: Boolean
Does the base type have initial value
Does the base type have initial value
- Definition Classes
- BaseType
- def hasOnlyOneStatement: Boolean
- Definition Classes
- StatementDoubleLinkedContainer
- def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean
- Definition Classes
- SpinalTagReady
- def hasTag(spinalTag: SpinalTag): Boolean
- Definition Classes
- SpinalTagReady
- def hashCode(): Int
- Definition Classes
- OverridedEqualsHashCode → AnyRef → Any
- def head: AssignmentStatement
- Definition Classes
- StatementDoubleLinkedContainer
- def high: Int
Return the upper bound
Return the upper bound
- Definition Classes
- BitVector
- def init(that: SInt): SInt
Set initial value of the signal
Set initial value of the signal
- Definition Classes
- DataPrimitives
- final def initFrom(that: AnyRef, target: AnyRef = this): Unit
- Definition Classes
- Data
- def initNull(that: SInt): SInt
- Definition Classes
- DataPrimitives
- def initZero(): SInt
- Definition Classes
- DataPrimitives
- def initial(that: SInt): SInt
- Definition Classes
- BaseTypePrimitives
- def initialFrom(that: AnyRef, target: AnyRef = this): Unit
- Definition Classes
- BaseType
- def insertNext(s: Statement): Unit
- Definition Classes
- Statement
- def instanceAttributes(language: Language): Iterable[Attribute]
- Definition Classes
- SpinalTagReady
- def instanceAttributes: Iterable[Attribute]
- Definition Classes
- SpinalTagReady
- def isAnalog: Boolean
- def isComb: Boolean
- def isCompletelyUnnamed: Boolean
- Definition Classes
- Nameable
- def isDirectionLess: Boolean
- Definition Classes
- Data
- def isEmptyOfTag: Boolean
- Definition Classes
- SpinalTagReady
- def isFrozen(): Boolean
- Definition Classes
- BaseType
- def isInOut: Boolean
- Definition Classes
- Data
- def isInput: Boolean
- Definition Classes
- Data
- def isInputOrInOut: Boolean
- Definition Classes
- Data
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- final def isNamed: Boolean
- Definition Classes
- Nameable
- def isOutput: Boolean
- Definition Classes
- Data
- def isOutputOrInOut: Boolean
- Definition Classes
- Data
- def isPriorityApplicable(namePriority: Byte): Boolean
- Definition Classes
- Nameable
- def isReg: Boolean
- def isRegOnAssign: Boolean
- def isTypeNode: Boolean
Is the baseType a node
Is the baseType a node
- Definition Classes
- BaseType
- def isUnknown: Bool
- Definition Classes
- BitVector
- def isUnnamed: Boolean
- Definition Classes
- NameableByComponent → Nameable
- def isUsingResetSignal: Boolean
Is the basetype using reset signal
Is the basetype using reset signal
- Definition Classes
- BaseType
- def isUsingSoftResetSignal: Boolean
Is the basetype using soft reset signal
Is the basetype using soft reset signal
- Definition Classes
- BaseType
- def isVital: Boolean
Check if the baseType is vital
Check if the baseType is vital
- Definition Classes
- BaseType
- val lastScopeStatement: Statement
- Definition Classes
- Statement
- def lsb: Bool
Return the least significant bit
Return the least significant bit
- Definition Classes
- BitVector
- def max(right: SInt): SInt
Return the hardware maximum value between this and right
Return the hardware maximum value between this and right
- Definition Classes
- Num
- def maxValue: BigInt
- Definition Classes
- SInt → MinMaxProvider
- def min(right: SInt): SInt
Return the hardware minimum value between this and right
Return the hardware minimum value between this and right
- Definition Classes
- Num
- def minValue: BigInt
- Definition Classes
- SInt → MinMaxProvider
- def msb: Bool
Return the most significant bit
Return the most significant bit
- Definition Classes
- BitVector
- def mux[T2 <: Data](mappings: (Any, T2)*): T2
Use a SpinalHDL data as a selector for a mux.
Use a SpinalHDL data as a selector for a mux.
- Definition Classes
- BaseType
- See also
- def muxDc[T2 <: Data](mappings: (Any, T2)*): T2
Version of SpinalHDL
muxthat allows Don't Care.Version of SpinalHDL
muxthat allows Don't Care.- Definition Classes
- BaseType
- See also
- def muxList[T2 <: Data](defaultValue: T2, mappings: Seq[(Any, T2)]): T2
Use a
scala.Seqof SpinalHDL data as mux inputs.Use a
scala.Seqof SpinalHDL data as mux inputs.- Definition Classes
- BaseType
- See also
- def muxList[T2 <: Data](mappings: Seq[(Any, T2)]): T2
Use a
scala.Seqof SpinalHDL data as mux inputs.Use a
scala.Seqof SpinalHDL data as mux inputs.- Definition Classes
- BaseType
- See also
- def muxListDc[T2 <: Data](mappings: Seq[(Any, T2)]): T2
Version of SpinalHDL
muxListthat allows Don't Care.Version of SpinalHDL
muxListthat allows Don't Care.- Definition Classes
- BaseType
- See also
- val name: String
- Definition Classes
- Nameable
- val nameableRef: Nameable
- def nandR: Bool
Hardware logical NAND of all bits
Hardware logical NAND of all bits
- Definition Classes
- BitVector
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def newExtract(offset: UInt, size: Int, extract: BitVectorRangedAccessFloating)(implicit loc: Location): SInt.this.type
Extract a range of bits of the BitVector
Extract a range of bits of the BitVector
- Definition Classes
- BitVector
- def newExtract(hi: Int, lo: Int, accessFactory: => BitVectorRangedAccessFixed): SInt.this.type
Extract a range of bits of the BitVector
Extract a range of bits of the BitVector
- Definition Classes
- BitVector
- def newExtract(bitId: UInt, extract: BitVectorBitAccessFloating): Bool
Extract a bit of the BitVector
Extract a bit of the BitVector
- Definition Classes
- BitVector
- def newExtract(bitId: Int, extract: BitVectorBitAccessFixed): Bool
Extract a bit of the BitVector
Extract a bit of the BitVector
- Definition Classes
- BitVector
- val nextScopeStatement: Statement
- Definition Classes
- Statement
- def noBackendCombMerge(): SInt.this.type
Put the combinatorial logic driving this signal in a separate process
Put the combinatorial logic driving this signal in a separate process
- Definition Classes
- Data
- def noCombLoopCheck(): SInt.this.type
Disable combinatorial loop checking for this Data
Disable combinatorial loop checking for this Data
- Definition Classes
- Data
- See also
- def norR: Bool
Hardware logical NOR of all bits
Hardware logical NOR of all bits
- Definition Classes
- BitVector
- def normalizeInputs: Unit
- Definition Classes
- BaseType → ExpressionContainer
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @HotSpotIntrinsicCandidate() @native()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @HotSpotIntrinsicCandidate() @native()
- def nxorR: Bool
Hardware logical NXOR of all bits
Hardware logical NXOR of all bits
- Definition Classes
- BitVector
- def onEachAttributes(doIt: (Attribute) => Unit): Unit
- Definition Classes
- SpinalTagReady
- def opName: String
- Definition Classes
- SInt → Expression
- def orMask(that: Bool): SInt.this.type
- Definition Classes
- BitVector
- def orR: Bool
Hardware logical OR of all bits
Hardware logical OR of all bits
Equivalent to
this.asBits =/= 0.- Definition Classes
- BitVector
- def overrideLocalName(name: String): SInt.this.type
- Definition Classes
- Nameable
- val parent: Data
- Definition Classes
- Data
- val parentScope: ScopeStatement
- Definition Classes
- ContextUser
- def pull(propagateName: Boolean): SInt.this.type
- Definition Classes
- Data
- def pull(): SInt.this.type
Pull a signal to the top level (use for debugging)
Pull a signal to the top level (use for debugging)
- Definition Classes
- Data
- def purify(): SInt.this.type
- Definition Classes
- Data
- def randBoot(u: Unit): SInt.this.type
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
- Definition Classes
- Data
- val refOwner: RefOwnerType
- Definition Classes
- OwnableRef
- Annotations
- @DontName()
- def reflectNames(): Unit
- Definition Classes
- Nameable
- def remapClockDomain(func: (ClockDomain) => ClockDomain): Unit
- def remapDrivingExpressions(func: (Expression) => Expression): Unit
- Definition Classes
- ExpressionContainer
- def remapExpressions(func: (Expression) => Expression): Unit
- Definition Classes
- DeclarationStatement → ExpressionContainer
- def removeAssignments(data: Boolean = true, init: Boolean = true, initial: Boolean = true): SInt.this.type
Remove all assignments of the base type
- def removeDataAssignments(): SInt.this.type
- Definition Classes
- Data
- def removeInitAssignments(): SInt.this.type
- Definition Classes
- Data
- def removeStatement(): Unit
- def removeStatementFromScope(): Unit
- Definition Classes
- Statement
- def removeTag(spinalTag: SpinalTag): SInt.this.type
- Definition Classes
- SpinalTagReady
- def removeTags(tags: Iterable[SpinalTag]): SInt.this.type
- Definition Classes
- SpinalTagReady
- def resize(width: BitCount): SInt
Return a resized copy of x.
- def resize(width: Int): SInt.this.type
Return a resized copy of x.
- def resized: SInt.this.type
Return a version of the signal which is allowed to be automatically resized where needed.
Return a version of the signal which is allowed to be automatically resized where needed.
The resize operation is deferred until the point of assignment later. The resize may widen or truncate, retaining the LSB.
- Definition Classes
- Data
- See also
- def reversed: SInt.this.type
- def rootIF(): Interface
root interface
root interface
- Definition Classes
- Data
- def rootIFList(): List[Interface]
- Definition Classes
- Data
- def rootIFrec(now: Data, lastRoot: List[Interface]): List[Interface]
- Definition Classes
- Data
- def rootScopeStatement: ScopeStatement
- def rotateLeft(that: Int): SInt
Left rotation of that bits
- def rotateLeft(that: UInt): T
Left rotation of that Bits
Left rotation of that Bits
- Definition Classes
- BitVector
- def rotateRight(that: Int): SInt
Right rotation of that bits
- def rotateRight(that: UInt): T
Right rotation of that Bits
Right rotation of that Bits
- Definition Classes
- BitVector
- def round(n: Int, align: Boolean = true): SInt
- def round(width: BitCount, align: Boolean): SInt
- Definition Classes
- Num
- def roundDown(n: Int, align: Boolean): SInt
SInt roundDown lowest m bits, complex for hardware , not recommended The algorithm represented by python code : ceil(x - 0.5)
- def roundDown(width: BitCount, align: Boolean): SInt
- Definition Classes
- Num
- def roundToEven(n: Int, align: Boolean): SInt
- def roundToEven(width: BitCount, align: Boolean): SInt
- Definition Classes
- Num
- def roundToInf(n: Int, align: Boolean = true): SInt
SInt roundToInf sign * floor(abs(x) + 0.5)
- def roundToInf(width: BitCount, align: Boolean): SInt
- Definition Classes
- Num
- def roundToOdd(n: Int, align: Boolean): SInt
- def roundToOdd(width: BitCount, align: Boolean): SInt
- Definition Classes
- Num
- def roundToZero(n: Int, align: Boolean): SInt
SInt roundToZero The algorithm represented by python code : sign * ceil(abs(x) - 0.5)
- def roundToZero(width: BitCount, align: Boolean): SInt
- Definition Classes
- Num
- def roundUp(n: Int, align: Boolean = true): SInt
SInt roundUp lowest m bits, friendly for hardware timing and area floor(x + 0.5)
- def roundUp(width: BitCount, align: Boolean): SInt
- Definition Classes
- Num
- def sat(m: Int): SInt
Saturation highest m bits
- def sat(width: BitCount): SInt
- Definition Classes
- Num
- def satWithSym(m: Int): SInt
- val scalaTrace: Throwable
- Definition Classes
- ScalaLocated
- def setAll(): SInt.this.type
Set all bits
- def setAllTo(value: Bool): SInt.this.type
Set all bits to value
Set all bits to value
- Definition Classes
- BitVector
- def setAllTo(value: Boolean): SInt.this.type
Set all bits to value
Set all bits to value
- Definition Classes
- BitVector
- def setAsAnalog(): SInt.this.type
- def setAsComb(): SInt.this.type
Set baseType to Combinatorial
- def setAsDirectionLess(): SInt.this.type
Remove the direction (
in,out,inout) to a signal - def setAsReg(): SInt.this.type
Set baseType to reg
- def setAsTypeNode(): SInt.this.type
Set baseType to Node
Set baseType to Node
- Definition Classes
- BaseType
- def setAsVital(): SInt.this.type
Set the baseType to vital
Set the baseType to vital
- Definition Classes
- BaseType
- def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): SInt.this.type
- Definition Classes
- Nameable
- def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): SInt.this.type
- Definition Classes
- Nameable
- def setCompositeName(nameable: Nameable, postfix: String): SInt.this.type
- Definition Classes
- Nameable
- def setCompositeName(nameable: Nameable, namePriority: Byte): SInt.this.type
- Definition Classes
- Nameable
- def setCompositeName(nameable: Nameable, weak: Boolean): SInt.this.type
- Definition Classes
- Nameable
- def setCompositeName(nameable: Nameable): SInt.this.type
- Definition Classes
- Nameable
- def setLambdaName(isNameBody: => Boolean)(nameGen: => String): SInt.this.type
- Definition Classes
- Nameable
- def setName(name: String, namePriority: Byte): SInt.this.type
- Definition Classes
- Nameable
- def setName(name: String, weak: Boolean): SInt.this.type
- Definition Classes
- Nameable
- def setName(name: String): SInt.this.type
- Definition Classes
- Nameable
- def setNameAsWeak(): SInt.this.type
- Definition Classes
- Nameable
- def setOutputAsReg(): SInt.this.type
Recursively set baseType to reg only for output
Recursively set baseType to reg only for output
- Definition Classes
- Data
- def setPartialName(name: String, namePriority: Byte, owner: Any): SInt.this.type
- Definition Classes
- Nameable
- def setPartialName(name: String, namePriority: Byte): SInt.this.type
- Definition Classes
- Nameable
- def setPartialName(name: String, weak: Boolean): SInt.this.type
- Definition Classes
- Nameable
- def setPartialName(owner: Nameable, name: String, namePriority: Byte): SInt.this.type
- Definition Classes
- Nameable
- def setPartialName(owner: Nameable, name: String, weak: Boolean): SInt.this.type
- Definition Classes
- Nameable
- def setPartialName(name: String): SInt.this.type
- Definition Classes
- Nameable
- def setPartialName(owner: Nameable, name: String): SInt.this.type
- Definition Classes
- Nameable
- def setPartialName(owner: Nameable): SInt.this.type
- Definition Classes
- Nameable
- def setRefOwner(that: Any): Unit
- Definition Classes
- OwnableRef
- def setScalaLocated(source: ScalaLocated): SInt.this.type
- Definition Classes
- ScalaLocated
- def setWeakName(name: String): SInt.this.type
- Definition Classes
- Nameable
- def setWidth(width: Int): SInt.this.type
Set the width of the BitVector
Set the width of the BitVector
- width
the width of the data
- returns
the BitVector of a given size
- Definition Classes
- BitVector
- def sign: Bool
- def simplifyNode: Expression
- Definition Classes
- Expression
- def sliceBy(divisor: List[Int]): List[Bits]
- Definition Classes
- BitVector
- def sliceBy(divisor: Int*): List[Bits]
apart by a list of width
apart by a list of width
- returns
(List(A(1 downto 0), A(2 downto 4), A(9 downto 3))
- Definition Classes
- BitVector
val res = A.sliceBy(2, 3, 5) val res = A.sliceBy(List(2, 3, 5))
Example: - def spinalTags: LinkedHashSet[SpinalTag]
- Definition Classes
- SpinalTagReady
- def splitAt(n: Int): (Bits, Bits)
Split at n st bits
Split at n st bits
- returns
(data10bits(8 downto 4), data10bits(3 downto 0))
- Definition Classes
- BitVector
val res = data10bits.splitAt(4)
Example: - def stabilized(func: (Expression) => Expression, seed: Expression): Expression
- Definition Classes
- ExpressionContainer
- def subdivideIn(sliceWidth: BitCount): Vec[T]
- Definition Classes
- BitVector
- def subdivideIn(sliceCount: SlicesCount): Vec[T]
- Definition Classes
- BitVector
- def subdivideIn(sliceWidth: BitCount, strict: Boolean): Vec[T]
Split the BitVector into slice of x bits
Split the BitVector into slice of x bits
- sliceWidth
the width of the slice
- strict
allow
subdivideInto generate vectors with varying size- returns
a Vector of slices
- Definition Classes
- BitVector
val res = myBits.subdivideIn(3 bits)
Example: - def subdivideIn(sliceCount: SlicesCount, strict: Boolean): Vec[T]
Split the BitVector into x slice
Split the BitVector into x slice
- sliceCount
the width of the slice
- strict
allow
subdivideInto generate vectors with varying size- returns
a Vector of slices
- Definition Classes
- BitVector
val res = myBits.subdivideIn(3 slices)
Example: - def switchAssign[T2 <: BaseType](sel: T2)(mappings: (Any, SInt)*): Unit
- Definition Classes
- DataPrimitives
- def symmetry: SInt
SIntsymmetricSIntsymmetric- returns
return a
SIntwhich minValue equal -maxValue
val symmetrySInt = mySInt.symmetry
Example: - final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- def tag(q: QFormat): SInt
- def take(n: Int): Bits
Take lowest n bits
Take lowest n bits
- returns
data10bits(3 downto 0)
- Definition Classes
- BitVector
val res = data10bits.take(4)
Example: - def takeHigh(n: Int): Bits
Take highest n bits
Take highest n bits
- returns
data10bits(9 downto 6)
- Definition Classes
- BitVector
val res = data10bits.takeHigh(4)
Example: - def takeLow(n: Int): Bits
- Definition Classes
- BitVector
- def toIo(): SInt.this.type
- Definition Classes
- Data
- def toMuxInput[T <: Data](muxOutput: T): T
- Definition Classes
- Data
- def toString(): String
- Definition Classes
- BitVector → BaseType → Expression → Nameable → AnyRef → Any
- def toStringMultiLine(): String
- Definition Classes
- BaseNode
- def toStringRec(level: Int = 1): String
- Definition Classes
- Expression
- def trim(m: Int): SInt
Discard the highest
mbits - def trim(width: BitCount): SInt
- Definition Classes
- Num
- def twoComplement(enable: Bool, plusOneEnable: Bool = null): SInt
- def unary_-: SInt
Negative number
Negative number
- returns
return a negative number
val result = -mySInt
Example: - def unary_~: SInt
Inverse bitwise operator
- def unfreeze(): SInt.this.type
- def unsetName(): SInt.this.type
- Definition Classes
- Nameable
- def valueRange: Range
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- def walkDrivingExpressions(func: (Expression) => Unit): Unit
- Definition Classes
- ExpressionContainer
- def walkExpression(func: (Expression) => Unit): Unit
- Definition Classes
- ExpressionContainer
- def walkExpressionPostorder(func: (Expression) => Unit): Unit
- Definition Classes
- ExpressionContainer
- def walkParentTreeStatements(func: (TreeStatement) => Unit): Unit
- Definition Classes
- Statement
- def walkParentTreeStatementsUntilRootScope(func: (TreeStatement) => Unit): Unit
- Definition Classes
- Statement
- def walkRemapDrivingExpressions(func: (Expression) => Expression): Unit
- Definition Classes
- ExpressionContainer
- def walkRemapExpressions(func: (Expression) => Expression): Unit
- Definition Classes
- ExpressionContainer
- def wrapCast[T <: BaseType](result: T, node: Cast): T
- Definition Classes
- BaseType
- def wrapNext(): SInt.this.type
- Definition Classes
- Data
- def xorMask(that: Bool): SInt.this.type
- Definition Classes
- BitVector
- def xorR: Bool
Hardware logical XOR of all bits
Hardware logical XOR of all bits
Equivalent to
this.asBools.reduce(_ ^ _).- Definition Classes
- BitVector
- def |(right: SInt): SInt
Bitwise OR operator
- def |<<(that: UInt): SInt
Logical shift left (output width == input width)
- def |<<(that: Int): SInt
Logical shift left (output width == input width)
- def |>>(that: UInt): SInt
Logical shift Right (output width == input width)
- def |>>(that: Int): SInt
Logical shift right (output width == input width)
Logical shift right (output width == input width)
- that
the number of right shift
- returns
a Bits of width : w(this)
val result = myUInt |>> 4
Example:
Deprecated Value Members
- def asDirectionLess(): SInt.this.type
- Definition Classes
- Data
- Annotations
- @deprecated
- Deprecated
(Since version ???) use setAsDirectionLess instead
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
(Since version 9)
- def genIf(cond: Boolean): SInt.this.type
Generate this if condition is true
Generate this if condition is true
- Definition Classes
- Data
- Annotations
- @deprecated
- Deprecated
does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead
- def range: Range
Return the range
Return the range
- Definition Classes
- BitVector
- Annotations
- @deprecated
- Deprecated
Use bitsRange instead