package core
- Alphabetic
- By Inheritance
- core
- BaseTypeCast
- UFixCast
- SFixCast
- BaseTypeFactory
- UFixFactory
- SFixFactory
- TypeFactory
- VecFactory
- SIntFactory
- UIntFactory
- BitsFactory
- BoolFactory
- AnyRef
- Any
- Hide All
- Show All
- Public
- Protected
Package Members
Type Members
- class AFix extends MultiData with Num[AFix] with BitwiseOp[AFix] with MinMaxDecimalProvider
- trait AllowIoBundle extends AnyRef
- trait Area extends NameableByComponent with ContextUser with OwnableRef with ScalaLocated with ValCallbackRec with OverridedEqualsHashCode
Sometime, creating a
Component
to define some logic is overkill.Sometime, creating a
Component
to define some logic is overkill. For this kind of cases you can useArea
to define a group of signals/logic.val tickConter = new Area{ val tick = Reg(UInt(8 bits) init(0) tick := tick + 1 }
- See also
Example: - trait AreaObject extends Area
- trait AreaRoot extends Area
- trait AssertNodeSeverity extends AnyRef
- trait Assignable extends AnyRef
Assignable trait
- trait Attribute extends SpinalTag
- class AttributeFlag extends Attribute
- class AttributeInteger extends Attribute
- sealed trait AttributeKind extends AnyRef
- class AttributeString extends Attribute
- abstract class BaseType extends Data with DeclarationStatement with StatementDoubleLinkedContainer[BaseType, AssignmentStatement] with Expression
Abstract base class of all Spinal types
- trait BaseTypeCast extends SFixCast with UFixCast
Base type Cast
- trait BaseTypeFactory extends BoolFactory with BitsFactory with UIntFactory with SIntFactory with VecFactory with SFixFactory with UFixFactory
Base type factory
- class BaseTypePimper[T <: BaseType] extends AnyRef
- trait BaseTypePrimitives[T <: BaseType] extends AnyRef
- implicit class BigDecimalBuilder extends AnyRef
BigDecimal Builder
- case class BigIntBuilder(i: BigInt) extends Product with Serializable
BigInt Builder
- case class BitCount(value: Int) extends Product with Serializable
Represent the number of bit of a data
- abstract class BitVector extends BaseType with Widthable
BitVector
is a family of types for storing multiple bits of information in a single value.BitVector
is a family of types for storing multiple bits of information in a single value. This type has three subtypes that can be used to model different behaviors:Bits
UInt
(unsigned integer)SInt
(signed integer)
- See also
- abstract class BitVectorLiteralFactory[T <: BitVector] extends AnyRef
Base class to create Bit Vector from literal
- class Bits extends BitVector with DataPrimitives[Bits] with BaseTypePrimitives[Bits] with BitwiseOp[Bits]
The
Bits
type corresponds to a vector of bits that does not convey any arithmetic meaning.The
Bits
type corresponds to a vector of bits that does not convey any arithmetic meaning.val myBits1 = Bits(32 bits) val myBits2 = B(25, 8 bits) val myBits3 = B"8'xFF" val myBits4 = B"1001_0011
- See also
Example: - trait BitsFactory extends AnyRef
Bits factory used for instance by the IODirection to create a in/out Bits
- trait BitwiseOp[T <: Data] extends AnyRef
Bitwise Operation
Bitwise Operation
- T
the type which is associated with the bitwise operation
- abstract class BlackBox extends Component
A blackbox allows the user to integrate an existing VHDL/Verilog component into the design by just specifying the interfaces.
A blackbox allows the user to integrate an existing VHDL/Verilog component into the design by just specifying the interfaces.
class Ram_1w_1r(wordWidth: Int, wordCount: Int) extends BlackBox { val generic = new Generic { val wordCount = Ram_1w_1r.this.wordCount val wordWidth = Ram_1w_1r.this.wordWidth } val io = new Bundle { val clk = in Bool() val wr = new Bundle { val en = in Bool() val addr = in UInt (log2Up(wordCount) bit) val data = in Bits (wordWidth bit) } val rd = new Bundle { val en = in Bool() val addr = in UInt (log2Up(wordCount) bit) val data = out Bits (wordWidth bit) } } mapClockDomain(clock=io.clk) }
Example: - class BlackBoxImpl extends AnyRef
- abstract class BlackBoxULogic extends BlackBox
Create a blackBox with std_ulogic instead of std_logic
- class Bool extends BaseType with DataPrimitives[Bool] with BaseTypePrimitives[Bool] with BitwiseOp[Bool]
The
Bool
type corresponds to a hardware boolean value (True
orFalse
)The
Bool
type corresponds to a hardware boolean value (True
orFalse
)val myBool = Bool() myBool := False myBool := Bool(false)
- See also
Example: - case class BoolEdges() extends Bundle with Product with Serializable
Bundle for the edge detection
- trait BoolFactory extends AnyRef
Bool
factory used for instance by the IODirection to create a in/out Bool() - class Bundle extends MultiData with Nameable with ValCallbackRec
A
Bundle
is a composite type that defines a group of named signals (of any SpinalHDL basic type) under a single name.A
Bundle
is a composite type that defines a group of named signals (of any SpinalHDL basic type) under a single name. ABundle
can be used to model data structures, buses and interfaces.val cmd = new Bundle{ val init = in Bool() val start = in Bool() val result = out Bits(32 bits) }
- See also
Example: - class BundleCase extends Bundle
- case class ClockDomain(clock: Bool, reset: Bool = null, dummyArg: DummyTrait = null, softReset: Bool = null, clockEnable: Bool = null, config: ClockDomainConfig = GlobalData.get.commonClockConfig, frequency: ClockFrequency = UnknownFrequency(), clockEnableDivisionRate: DivisionRate = ClockDomain.UnknownDivisionRate()) extends SpinalTagReady with Product with Serializable
Clock and reset signals can be combined to create a clock domain.
Clock and reset signals can be combined to create a clock domain.
Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain. Clock domain application work like a stack, which mean, if you are in a given clock domain, you can still apply another clock domain locally
- See also
- sealed trait ClockDomainBoolTag extends SpinalTag
- case class ClockDomainConfig(clockEdge: EdgeKind = RISING, resetKind: ResetKind = ASYNC, resetActiveLevel: Polarity = HIGH, softResetActiveLevel: Polarity = HIGH, clockEnableActiveLevel: Polarity = HIGH) extends Product with Serializable
- case class ClockDomainReportTag(clockDomain: ClockDomain) extends SpinalTag with Product with Serializable
- case class ClockDomainTag(clockDomain: ClockDomain) extends SpinalTag with Product with Serializable
- case class ClockDrivedTag(driver: Bool) extends SpinalTag with Product with Serializable
- case class ClockDriverTag(drived: Bool) extends SpinalTag with Product with Serializable
- class ClockEnableArea extends Area with PostInitCallback
Clock Area with a special clock enable.
Clock Area with a special clock enable.
- See also
- case class ClockEnableTag(clockDomain: ClockDomain) extends ClockDomainBoolTag with Product with Serializable
- case class ClockSyncTag(a: Bool, b: Bool) extends SpinalTag with Product with Serializable
- case class ClockTag(clockDomain: ClockDomain) extends ClockDomainBoolTag with Product with Serializable
- class ClockingArea extends Area with PostInitCallback
Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain.
Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain.
- See also
- class CommentTag extends SpinalTag
- abstract class Component extends NameableByComponent with ContextUser with ScalaLocated with PostInitCallback with Stackable with OwnableRef with SpinalTagReady with OverridedEqualsHashCode with ValCallbackRec
Abstract class used to create a new
Component
Abstract class used to create a new
Component
class MyAndGate extends Component { val io = new Bundle{ val a,b = in Bool() val res = out Bool() } io.res := io.a & io.b }
- See also
Example: - class Composite[T <: Nameable] extends Area
- trait ConditionalContext extends GlobalDataUser
- trait ContextUser extends GlobalDataUser with ScalaLocated
- class CrossClockBufferDepth extends SpinalTag
- case class CyclesCount(value: BigInt) extends Product with Serializable
Cycles number representation
- trait Data extends ContextUser with NameableByComponent with Assignable with SpinalTagReady with GlobalDataUser with ScalaLocated with OwnableRef with OverridedEqualsHashCode with InComponent
- class DataPimper[T <: Data] extends DataPrimitives[T]
Should not extends AnyVal, Because it create kind of strange call stack move that make error reporting miss accurate
- trait DataPrimitives[T <: Data] extends AnyRef
- trait DataWrapper extends Data
- class DefaultTag extends SpinalTag
- case class Device(vendor: String = "?", family: String = "?", name: String = "?", supportBootResetKind: Boolean = true) extends Product with Serializable
target device
- trait DontName extends Annotation
- Annotations
- @Retention()
- case class DoubleBuilder(d: Double) extends Product with Serializable
Double Builder
- trait DummyTrait extends AnyRef
- case class DumpWaveConfig(depth: Int = 0, vcdPath: String = "wave.vcd") extends Product with Serializable
- trait DuringWritePolicy extends AnyRef
- sealed trait EdgeKind extends AreaObject
- class ElseWhenClause extends AnyRef
- implicit class ElseWhenClauseBuilder extends AnyRef
Implicit clause builder for
elseWhen
- sealed trait Endianness extends AnyRef
Endianness enumeration
- class EnumLiteral[T <: SpinalEnum] extends Literal with InferableEnumEncodingImpl
Node representation which contains the value of an SpinalEnumElement
- class EnumPoison extends Literal with InferableEnumEncodingImpl
- case class ExpNumber(value: Int) extends Product with Serializable
Exponent representation
- class ExternalDriverTag extends SpinalTag
- case class FixPointConfig(roundType: RoundType, symmetric: Boolean) extends Product with Serializable
- type FixedFrequency = core.ClockDomain.FixedFrequency
- class GenerationFlags extends AnyRef
- class Generic extends AnyRef
Create a generic for a BlackBox
Create a generic for a BlackBox
class myMemory(sizeMem: Int) extends BlackBox{ val generic = new Generic{ val size = sizeMem } val io = new Bundle { ... } }
Example: - case class GenericValue(e: Expression) extends SpinalTag with Product with Serializable
- class GlobalData extends AnyRef
Global data
- trait GlobalDataUser extends AnyRef
Get a link to the globalData
- class HardMap extends MultiData
- class HardType[T <: Data] extends OverridedEqualsHashCode
- case class HertzNumber(v: BigDecimal) extends PhysicalNumber[HertzNumber] with Product with Serializable
Frequency representation
- type IClockDomainFrequency = ClockFrequency
- trait IConnectable[T <: IConnectable[T]] extends AnyRef
- sealed trait IODirection extends BaseTypeFactory
Declare ports
Declare ports
A port is some Data with a direction, which can be
in
,out
orinout
.There are 4 available syntaxes, which are all equivalent:
val braces = in(Vec(Bool, 5)) val short = in Vec (Bool, 5) val spaceful = in port Vec(Bool, 5) val variadic = Vec(Bool, 5) in(variadic)
The "braces" syntax is short and generic, but it uses braces.
The "short" syntax is short, but it is formatted with a space between the type and its parameters, and it can be used only with:
Bool
Bits
UInt
SInt
Vec
The "spaceful" syntax is generic and beautiful, but more verbose.
The "variadic" syntax can be used with any number of ports, but can be used only if the ports types are already declared.
- class IfDefTag extends SpinalTag
- abstract class ImplicitArea[T] extends Area
Create an Area which can be assign to a data
Create an Area which can be assign to a data
class Counter extends ImplicitArea[UInt]{ val cnt = Reg(UInt(8 bits) ... override def implicitValue: UInt = cnt } val myCounter = Counter() io.myUInt = myCounter
Example: - trait InComponent extends AnyRef
- final class IntBuilder extends AnyVal
Integer Builder
- class Interface extends Bundle
system verilog interface
system verilog interface
Example
case class MyIf(width: Int = 8) extends Interface with IMasterSlave { val wParam = addGeneric("WIDTH", width, default = "8") val a = Bits(width bits) tieGeneric(a, wParam) val b = Bool() val c = SInt(8 bits) override def asMaster = mst @modport def mst = { out(a, b, c) } @modport def slv = { in(a, b, c) } }
- sealed trait Language extends AnyRef
- implicit class LiteralBuilder extends AnyRef
Literal builder
Literal builder
S/U/B"[[size']base]value"
e.g.:
B"8'xFF"`
- class MaskedBoolean extends AnyRef
Masked Literal
Masked Literal
val itMatch = myBits === M"00--10--" // - don't care value
Example: - class MaskedLiteral extends AnyRef
- class Mem[T <: Data] extends DeclarationStatement with StatementDoubleLinkedContainer[Mem[_], MemPortStatement] with WidthProvider with SpinalTagReady with InComponent
- trait MemBlackboxingPolicy extends AnyRef
- trait MemPortStatement extends LeafStatement with StatementDoubleLinkedContainerElement[Mem[_], MemPortStatement] with Nameable with SpinalTagReady
- class MemReadAsync extends MemPortStatement with WidthProvider with ContextUser with Expression
- class MemReadSync extends MemPortStatement with WidthProvider with ContextUser with Expression
- class MemReadWrite extends MemPortStatement with WidthProvider with ContextUser with Expression
- case class MemSymbolesMapping(name: String, range: Range) extends Product with Serializable
- case class MemSymbolesTag(mapping: Seq[MemSymbolesMapping]) extends SpinalTag with Product with Serializable
- trait MemTechnologyKind extends AnyRef
- class MemWrite extends MemPortStatement with WidthProvider
- class MemWritePayload[T <: Data] extends Bundle
- trait MinMaxDecimalProvider extends AnyRef
- trait MinMaxProvider extends AnyRef
Min max base function
- type Module = Component
- abstract class MultiData extends Data
Base class for multi data like Vec, Bundle
- trait Nameable extends OwnableRef with ContextUser
- trait NameableByComponent extends Nameable with GlobalDataUser
- class NamedType[T <: Data] extends HardType[T] with Nameable
- class NamingScope extends AnyRef
- trait Num[T <: Data] extends AnyRef
Base operations for numbers
Base operations for numbers
- T
the type which is associated with the base operation
- trait OverridedEqualsHashCode extends AnyRef
- trait OwnableRef extends AnyRef
- abstract class PhysicalNumber[T <: PhysicalNumber[_]] extends Formattable
Base class for the Physical representation (Hertz, Time, ...)
Base class for the Physical representation (Hertz, Time, ...)
When formatting (e.g. via f-interpolation) one can use: - precision to specify precsion (e.g. "%.3f" for three digits past comma) - width to pad with space to a specified length (e.g. "%5f" to get at least 5 characters) - left justified padding (e.g. "%-5f" to pad right to 5 characters) - alternate to print w/o unit (e.g. "%#f")
- implicit final class PhysicalNumberPimper extends AnyVal
- sealed trait Polarity extends AreaObject
- case class PosCount(value: Int) extends Product with Serializable
Position representation
- case class QFormat(width: Int, fraction: Int, signed: Boolean) extends Product with Serializable
- class Ram_1w_1ra extends BlackBox
- class Ram_1w_1rs extends BlackBox
- class Ram_1wors extends BlackBox
- class Ram_1wrs extends BlackBox
- class Ram_2c_1w_1rs extends BlackBox
- class Ram_2wrs extends BlackBox
- class Ram_Generic extends BlackBox
- implicit class RangePimper extends AnyRef
Implicit Range helper
- trait ReadUnderWritePolicy extends AnyRef
- case class Ref[T](value: T) extends Product with Serializable
Use to give value by reference to a function
- class ResetArea extends Area with PostInitCallback
ResetArea
allow to reset an area with a special reset combining with the current reset (cumulative).ResetArea
allow to reset an area with a special reset combining with the current reset (cumulative).- See also
- sealed trait ResetKind extends AreaObject
- case class ResetTag(clockDomain: ClockDomain) extends ClockDomainBoolTag with Product with Serializable
- sealed trait RoundType extends AnyRef
- class SFix extends XFix[SFix, SInt]
Signed fix point
Signed fix point
- See also
- class SFix2D extends Bundle
- trait SFixCast extends AnyRef
- trait SFixFactory extends TypeFactory
- class SInt extends BitVector with Num[SInt] with MinMaxProvider with DataPrimitives[SInt] with BaseTypePrimitives[SInt] with BitwiseOp[SInt]
The
SInt
type corresponds to a vector of bits that can be used for signed integer arithmetic.The
SInt
type corresponds to a vector of bits that can be used for signed integer arithmetic.val mySInt = SInt(8 bits) mySInt := S(4, 8 bits) + S"0000_1111" mySInt := S(4) - S"h1A"
- See also
Example: - trait SIntFactory extends AnyRef
SInt
factory used for instance by theIODirection
to create a in/outSInt
- implicit class SIntPimper extends AnyRef
Implicit SInt helper
- class SafeStack[T] extends AnyRef
Safe Stack
- class SafeStackWithStackable[T <: Stackable] extends SafeStack[T]
- trait ScalaLocated extends GlobalDataUser
- class ScopeProperty[T] extends AnyRef
- class ScopePropertyContext extends AnyRef
- class ScopePropertyValue extends AnyRef
- case class SlicesCount(value: Int) extends Product with Serializable
Slice size representation
- class SlowArea extends ClockingArea
Define a clock domain which is x time slower than the current clock.
Define a clock domain which is x time slower than the current clock.
- See also
- case class SpinalConfig(mode: SpinalMode = null, flags: HashSet[Any] = mutable.HashSet[Any](), debugComponents: HashSet[Class[_]] = mutable.HashSet[Class[_]](), keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = SpinalConfig.defaultTargetDirectory, oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", privateNamespace: Boolean = false, formalAsserts: Boolean = false, anonymSignalPrefix: String = null, device: Device = Device(), inlineRom: Boolean = false, caseRom: Boolean = false, romReuse: Boolean = false, genVhdlPkg: Boolean = true, verbose: Boolean = false, mergeAsyncProcess: Boolean = false, mergeSyncProcess: Boolean = true, asyncResetCombSensitivity: Boolean = false, anonymSignalUniqueness: Boolean = false, inlineConditionalExpression: Boolean = false, nameWhenByFile: Boolean = true, genLineComments: Boolean = false, noRandBoot: Boolean = false, randBootFixValue: Boolean = true, noAssert: Boolean = false, fixToWithWrap: Boolean = true, headerWithDate: Boolean = false, headerWithRepoHash: Boolean = true, removePruned: Boolean = false, allowOutOfRangeLiterals: Boolean = false, dontCareGenAsZero: Boolean = false, obfuscateNames: Boolean = false, normalizeComponentClockDomainName: Boolean = false, devicePhaseHandler: PhaseDeviceHandler = PhaseDeviceDefault, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) => Unit] = ArrayBuffer[(ArrayBuffer[Phase]) => Unit](), transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ArrayBuffer[Phase] (/*new PhaseMemBlackBoxerDefault(blackboxNothing)*/), rtlHeader: String = null, scopeProperties: LinkedHashMap[ScopeProperty[_], Any] = mutable.LinkedHashMap[ScopeProperty[_], Any](), _withEnumString: Boolean = true, enumPrefixEnable: Boolean = true, enumGlobalEnable: Boolean = false, bitVectorWidthMax: Int = 4096, singleTopLevel: Boolean = true, noAssertAtTimeZero: Boolean = false, cutLongExpressions: Boolean = true, withTimescale: Boolean = true, printFilelist: Boolean = true, emitFullComponentBindings: Boolean = true, svInterface: Boolean = false) extends Product with Serializable
Spinal configuration for the generation of the RTL
- class SpinalEnum extends Nameable with ScalaLocated
Base class for creating enumeration
Base class for creating enumeration
object MyEnum extends SpinalEnum(binarySequential){ val s1, s2, s3, s4 = newElement() }
SpinalEnum
contains a list ofSpinalEnumElement
that is the definition of an element.SpinalEnumCraft
is the hardware representation of the the element.- See also
Example: - class SpinalEnumCraft[T <: SpinalEnum] extends BaseType with InferableEnumEncodingImpl with BaseTypePrimitives[SpinalEnumCraft[T]] with DataPrimitives[SpinalEnumCraft[T]]
Hardware representation of an enumeration
- class SpinalEnumElement[T <: SpinalEnum] extends Nameable with SpinalTagReady
Definition of an element of the enumeration
- trait SpinalEnumEncoding extends Nameable with ScalaLocated
Trait to define an encoding
- class SpinalExit extends Exception
- trait SpinalMode extends AnyRef
- class SpinalReport[T <: Component] extends AnyRef
Spinal report give after the generation of the RTL
- abstract class SpinalStruct extends BaseType with Nameable with ValCallbackRec with DataPrimitives[SpinalStruct] with Suffixable
Class representing Verilog Struct and VHDL Record data types.
- trait SpinalTag extends AnyRef
- trait SpinalTagGetter[T] extends SpinalTag
- trait SpinalTagReady extends AnyRef
- trait Stackable extends AnyRef
- class SwitchContext extends AnyRef
- class TagAFixTruncated extends SpinalTag
- case class TimeNumber(v: BigDecimal) extends PhysicalNumber[TimeNumber] with Product with Serializable
Time representation
- sealed trait TimingEndpointType extends AnyRef
- class ToBitsPimper extends AnyRef
- implicit class Tuple10Pimper extends TuplePimperBase
- implicit class Tuple11Pimper extends TuplePimperBase
- implicit class Tuple12Pimper extends TuplePimperBase
- implicit class Tuple13Pimper extends TuplePimperBase
- implicit class Tuple14Pimper extends TuplePimperBase
- implicit class Tuple15Pimper extends TuplePimperBase
- implicit class Tuple16Pimper extends TuplePimperBase
- implicit class Tuple17Pimper extends TuplePimperBase
- implicit class Tuple18Pimper extends TuplePimperBase
- implicit class Tuple19Pimper extends TuplePimperBase
- implicit class Tuple20Pimper extends TuplePimperBase
- implicit class Tuple21Pimper extends TuplePimperBase
- implicit class Tuple22Pimper extends TuplePimperBase
- implicit class Tuple2Pimper extends TuplePimperBase
- implicit class Tuple3Pimper extends TuplePimperBase
- implicit class Tuple4Pimper extends TuplePimperBase
- implicit class Tuple5Pimper extends TuplePimperBase
- implicit class Tuple6Pimper extends TuplePimperBase
- implicit class Tuple7Pimper extends TuplePimperBase
- implicit class Tuple8Pimper extends TuplePimperBase
- implicit class Tuple9Pimper extends TuplePimperBase
- case class TupleBundle1[T1 <: Data](payloadType1: HardType[T1]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle10[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle11[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle12[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle13[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle14[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle15[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle16[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle17[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle18[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17], payloadType18: HardType[T18]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle19[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17], payloadType18: HardType[T18], payloadType19: HardType[T19]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle2[T1 <: Data, T2 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle20[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17], payloadType18: HardType[T18], payloadType19: HardType[T19], payloadType20: HardType[T20]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle21[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data, T21 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17], payloadType18: HardType[T18], payloadType19: HardType[T19], payloadType20: HardType[T20], payloadType21: HardType[T21]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle22[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data, T21 <: Data, T22 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17], payloadType18: HardType[T18], payloadType19: HardType[T19], payloadType20: HardType[T20], payloadType21: HardType[T21], payloadType22: HardType[T22]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle3[T1 <: Data, T2 <: Data, T3 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle4[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle5[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle6[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle7[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle8[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8]) extends TupleBundleBase with Product with Serializable
- case class TupleBundle9[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9]) extends TupleBundleBase with Product with Serializable
- class TupleBundleBase extends Bundle
- class TuplePimperBase extends AnyRef
- trait TypeFactory extends AnyRef
- class UFix extends XFix[UFix, UInt]
Unsigned fix point
Unsigned fix point
- See also
- class UFix2D extends Bundle
Two-dimensional XFix
- trait UFixCast extends AnyRef
- trait UFixFactory extends TypeFactory
- class UInt extends BitVector with Num[UInt] with MinMaxProvider with DataPrimitives[UInt] with BaseTypePrimitives[UInt] with BitwiseOp[UInt]
The
UInt
type corresponds to a vector of bits that can be used for unsigned integer arithmetic.The
UInt
type corresponds to a vector of bits that can be used for unsigned integer arithmetic.val myUInt = UInt(8 bits) myUInt := U(2,8 bits) myUInt := U(2) myUInt := U"0000_0101" myUInt := U"h1A"
- See also
Example: - case class UInt2D(xBitCount: BitCount, yBitCount: BitCount) extends Bundle with Product with Serializable
Define an
UInt
2D pointDefine an
UInt
2D point- xBitCount
width of the x point
- yBitCount
width of the y point
val positionOnScreen = Reg(UInt2D(log2Up(p.screenResX) bits, log2Up(p.screenResY) bits))
Example: - trait UIntFactory extends AnyRef
UInt factory used for instance by the IODirection to create a in/out UInt
- implicit class UIntPimper extends AnyRef
Implicit UInt helper
- class Union extends MultiData with PostInitCallback
- class UnionElement[T <: Data] extends AnyRef
- type UnknownFrequency = core.ClockDomain.UnknownFrequency
- trait ValCallbackRec extends ValCallback
- class VarAssignementTag extends SpinalTag
- class Vec[T <: Data] extends MultiData with IndexedSeq[T]
A
Vec
is a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single nameA
Vec
is a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single nameval myVecOfSInt = Vec(SInt(8 bits), 2)
- See also
Example: - class VecAccessAssign[T <: Data] extends Assignable
- class VecBitwisePimper[T <: Data with BitwiseOp[T]] extends BitwiseOp[Vec[T]]
- trait VecFactory extends AnyRef
Vec factory
- class VecBuilder extends AnyRef
- Definition Classes
- VecFactory
- case class VerilogValues(v: String) extends Product with Serializable
- class WhenContext extends ConditionalContext with ScalaLocated
Used by SpinalHDL
when
/elsewhen
/otherwise
andWhenBuilder
to keep track of the structure. - abstract class XFix[T <: XFix[T, R], R <: BitVector with Num[R]] extends MultiData with MinMaxDecimalProvider
Base class for SFix and UFix
- case class crossClockFalsePath(source: Option[BaseType] = None, destType: TimingEndpointType = TimingEndpointType.DATA) extends SpinalTag with Product with Serializable
- case class crossClockMaxDelay(cycles: Int, useTargetClock: Boolean) extends SpinalTag with Product with Serializable
- type dontName = spinal.core.DontName @scala.annotation.meta.field
- trait modport extends Annotation
- Annotations
- @Retention()
Value Members
- implicit def BaseTypePimped[T <: BaseType](that: T): BaseTypePimper[T]
- implicit def BigIntToBits(that: BigInt): Bits
- implicit def BigIntToBuilder(value: BigInt): BigIntBuilder
- implicit def BigIntToSInt(that: BigInt): SInt
- implicit def BigIntToUInt(that: BigInt): UInt
- def Bits(width: BitCount): Bits
Create a new Bits of a given width
Create a new Bits of a given width
- Definition Classes
- BitsFactory
- def Bits(u: Unit = ()): Bits
Create a new Bits
Create a new Bits
- Definition Classes
- BitsFactory
- def Bool(value: Boolean)(implicit loc: Location): Bool
Create a new
Bool
with a valueCreate a new
Bool
with a value- Definition Classes
- BoolFactory
- def Bool(u: Unit = ()): Bool
Create a new
Bool
Create a new
Bool
- Definition Classes
- BoolFactory
- implicit def BooleanPimped(that: Boolean): BooleanPimped
- implicit def DataPimped[T <: Data](that: T): DataPimper[T]
Implicit Data helper
- val DefaultFixPointConfig: FixPointConfig
- implicit def DoubleToBuilder(value: Double): DoubleBuilder
- implicit def EnumCtoEnumC2[T <: SpinalEnum, T2 <: T](craft: SpinalEnumCraft[T2]): SpinalEnumCraft[T]
- implicit def EnumCtoEnumC3[T <: SpinalEnum, T2 <: T](craft: SpinalEnumCraft[T]): SpinalEnumCraft[T2]
- implicit def EnumElementToCraft[T <: SpinalEnum](element: SpinalEnumElement[T]): SpinalEnumCraft[T]
- implicit def EnumEtoEnumE2[T <: SpinalEnum, T2 <: T](element: SpinalEnumElement[T2]): SpinalEnumElement[T]
Implicit senum conversion
- implicit def EnumEtoEnumE3[T <: SpinalEnum, T2 <: T](element: SpinalEnumElement[T]): SpinalEnumElement[T2]
- def False(implicit loc: Location): Bool
SpinalHDL false value
- def FixedFrequency(value: HertzNumber): core.ClockDomain.FixedFrequency
- implicit def IntPimped(that: Int): IntPimped
- implicit def IntToBits(that: Int): Bits
- implicit def IntToBuilder(value: Int): IntBuilder
Implicit Int/BigInt/Double to Builder
- implicit def IntToSInt(that: Int): SInt
- implicit def IntToUInt(that: Int): UInt
Implicit conversion from Int/BigInt/String to UInt/SInt/Bits
- implicit def LongToBits(that: Long): Bits
- implicit def LongToSInt(that: Long): SInt
- implicit def LongToUInt(that: Long): UInt
- val LowCostFixPointConfig: FixPointConfig
- def SFix(peak: ExpNumber, resolution: ExpNumber): SFix
- Definition Classes
- SFixFactory
- def SFix(peak: ExpNumber, width: BitCount): SFix
- Definition Classes
- SFixFactory
- def SInt(width: BitCount): SInt
Create a new SInt of a given width
Create a new SInt of a given width
- Definition Classes
- SIntFactory
- def SInt(u: Unit = ()): SInt
Create a new SInt
Create a new SInt
- Definition Classes
- SIntFactory
- def True(implicit loc: Location): Bool
SpinalHDL true value
- def UFix(peak: ExpNumber, resolution: ExpNumber): UFix
- Definition Classes
- UFixFactory
- def UFix(peak: ExpNumber, width: BitCount): UFix
- Definition Classes
- UFixFactory
- def UInt(width: BitCount): UInt
Create a new UInt of a given width
Create a new UInt of a given width
- Definition Classes
- UIntFactory
- def UInt(u: Unit = ()): UInt
Create a new UInt
Create a new UInt
- Definition Classes
- UIntFactory
- def UnknownFrequency(): core.ClockDomain.UnknownFrequency
- def Vec[T <: Data](firstElement: T, followingElements: T*): Vec[T]
- Definition Classes
- VecFactory
- def Vec[T <: Data](gen: HardType[T], size: Int): Vec[T]
- Definition Classes
- VecFactory
- def Vec[T <: Data](gen: => T, size: Int): Vec[T]
- Definition Classes
- VecFactory
- def Vec[T <: Data](elements: TraversableOnce[T], dataType: HardType[T] = null): Vec[T]
- Definition Classes
- VecFactory
- val Vec: VecBuilder
- Definition Classes
- VecFactory
- implicit def VecBitwisePimped[T <: Data with BitwiseOp[T]](that: Vec[T]): VecBitwisePimper[T]
- def assert(assertion: Bool, message: Seq[Any], severity: AssertNodeSeverity)(implicit loc: Location): AssertStatement
- def assert(assertion: Bool, message: String, severity: AssertNodeSeverity)(implicit loc: Location): AssertStatement
- def assert(assertion: Bool, message: Seq[Any])(implicit loc: Location): AssertStatement
- def assert(assertion: Bool, message: String)(implicit loc: Location): AssertStatement
- def assert(assertion: Bool, severity: AssertNodeSeverity)(implicit loc: Location): AssertStatement
- def assert(assertion: Bool)(implicit loc: Location): AssertStatement
- final def assert(assertion: Boolean, message: => Any)(implicit loc: Location): Unit
- Annotations
- @elidable() @inline()
- def assert(assertion: Boolean): Unit
Assertion
Assertion
- Annotations
- @elidable()
- def assume(assertion: Bool)(implicit loc: Location): AssertStatement
- def assumeInitial(assertion: Bool)(implicit loc: Location): AssertStatement
- def cover(assertion: Bool)(implicit loc: Location): AssertStatement
- implicit lazy val implicitConversions: implicitConversions
Scala implicit
- def postTypeFactory[T <: Data](that: T): T
- Definition Classes
- TypeFactory
- implicit lazy val postfixOps: postfixOps
- implicit lazy val reflectiveCalls: reflectiveCalls
- def report(message: Seq[Any], severity: AssertNodeSeverity): AssertStatement
- def report(message: String, severity: AssertNodeSeverity): AssertStatement
- def report(message: Seq[Any]): AssertStatement
- def report(message: String): AssertStatement
- implicit def tupleBunder10Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10)): TupleBundle10[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10]
- implicit def tupleBunder11Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11)): TupleBundle11[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11]
- implicit def tupleBunder12Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12)): TupleBundle12[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12]
- implicit def tupleBunder13Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13)): TupleBundle13[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13]
- implicit def tupleBunder14Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14)): TupleBundle14[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14]
- implicit def tupleBunder15Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15)): TupleBundle15[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15]
- implicit def tupleBunder16Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16)): TupleBundle16[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16]
- implicit def tupleBunder17Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17)): TupleBundle17[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17]
- implicit def tupleBunder18Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18)): TupleBundle18[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18]
- implicit def tupleBunder19Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19)): TupleBundle19[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19]
- implicit def tupleBunder20Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20)): TupleBundle20[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20]
- implicit def tupleBunder21Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data, T21 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21)): TupleBundle21[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21]
- implicit def tupleBunder22Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data, T21 <: Data, T22 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22)): TupleBundle22[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22]
- implicit def tupleBunder2Pimp[T1 <: Data, T2 <: Data](pimped: (T1, T2)): TupleBundle2[T1, T2]
- implicit def tupleBunder3Pimp[T1 <: Data, T2 <: Data, T3 <: Data](pimped: (T1, T2, T3)): TupleBundle3[T1, T2, T3]
- implicit def tupleBunder4Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data](pimped: (T1, T2, T3, T4)): TupleBundle4[T1, T2, T3, T4]
- implicit def tupleBunder5Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data](pimped: (T1, T2, T3, T4, T5)): TupleBundle5[T1, T2, T3, T4, T5]
- implicit def tupleBunder6Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data](pimped: (T1, T2, T3, T4, T5, T6)): TupleBundle6[T1, T2, T3, T4, T5, T6]
- implicit def tupleBunder7Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7)): TupleBundle7[T1, T2, T3, T4, T5, T6, T7]
- implicit def tupleBunder8Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8)): TupleBundle8[T1, T2, T3, T4, T5, T6, T7, T8]
- implicit def tupleBunder9Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9)): TupleBundle9[T1, T2, T3, T4, T5, T6, T7, T8, T9]
- object AF
- object AFix
- object AFixRounding extends ScopeProperty[TagAFixTruncated]
- object ASYNC extends ResetKind
- object AllowMixedWidth extends SpinalTag
- object AllowPartialyAssignedTag extends SpinalTag
- object Analog
Set a data to Analog
- object AnnotationUtils
- object ArrayManager
- object B extends BitVectorLiteralFactory[Bits]
Used to create a new Bits or cast to Bits
- object BIG extends Endianness
Big-Endian
- object BOOT extends ResetKind
- object BaseType
- object COMMENT_ATTRIBUTE extends AttributeKind
- object COMMENT_TYPE_ATTRIBUTE extends AttributeKind
- object Cat
Concatenate a list of data
- object ClassName
- object Clock
- object ClockDomain extends Serializable
- object ClockDomainStack extends ScopeProperty[Handle[ClockDomain]]
- object CombInit
Create a new signal, assigned by the given parameter.
Create a new signal, assigned by the given parameter.
Useful to provide a "copy" of something that you can then modify with more conditional assignments.
- See also
- object Component
- object ConditionalContext
- object ContextSwapper
- object CyclesCount extends Serializable
- object DEFAULT_ATTRIBUTE extends AttributeKind
- object Data
- object DataAssign
- object Device extends Serializable
- object Driver
- object DslScopeStack extends ScopeProperty[ScopeStatement]
- object DummyObject extends DummyTrait
- object ERROR extends AssertNodeSeverity
- object FAILURE extends AssertNodeSeverity
- object FALLING extends EdgeKind
- object FixPointProperty extends ScopeProperty[FixPointConfig]
- object GenerationFlags
- object GlobalData
- object Gray
- object HIGH extends Polarity
- object HardMap
- object HardType
- object ImplicitArea
- object Info
- object InitAssign
- object InitialAssign
- object IsInterface extends SpinalTag
- object LITTLE extends Endianness
Little-Endian
- object LOW extends Polarity
- object Language
- object Latch
- object LatchWhen
- object LocatedPendingError
- object LutInputs extends ScopeProperty[Int]
- object MaskedLiteral
- object Mem
- object MemReadAsync
- object MemReadSync
- object MemReadWrite
- object MemWrite
- object Mux
SpinalHDL standalone mux with
Bool
selectorSpinalHDL standalone mux with
Bool
selectorTypes like
Enum
/Bool
/Bits
/UInt
/SInt
can also be used as selector with the methodmux()
of their parentBaseType
.- See also
- object NOTE extends AssertNodeSeverity
- object Nameable
- object NamedType
- object OnCreateStack extends ScopeProperty[(Nameable) => Unit]
- object OwnableRef
- object PendingError
- object Pull
- object REPORT_TIME
- object RISING extends EdgeKind
- object Ram_1w_1ra
- object Ram_1w_1rs
- object Reg
Create a register
- object RegInit
Declare a register with an initialize value
- object RegNext
Register a signal of one clock
- object RegNextWhen
Register a signal when a condition is true
- object RoundType
- object S extends BitVectorLiteralFactory[SInt]
Used to create a new SInt or cast to SInt
- object SF
- object SFix2D
Two-dimensional
SFix
- object SQ
- object SYNC extends ResetKind
- object ScalaLocated
- object ScopeProperty
- object Select
- object Spinal
- object SpinalConfig extends Serializable
- object SpinalEnumEncoding
Used to create a custom encoding
Used to create a custom encoding
object BR extends SpinalEnum{ val NE, EQ, J, JR = newElement() defaultEncoding = SpinalEnumEncoding("opt")( EQ -> 0, NE -> 1, J -> 2, JR -> 3 ) }
Example: - object SpinalError
- object SpinalExit extends Serializable
- object SpinalInfo
- object SpinalLog
- object SpinalMap
Spinal map
- object SpinalProgress
- object SpinalSystemVerilog
- object SpinalTagReady
- object SpinalVerilog
- object SpinalVhdl
- object SpinalWarning
- object SwitchStack extends ScopeProperty[SwitchContext]
- object SystemVerilog extends SpinalMode
- object TimingEndpointType
- object TupleBundle
- object U extends BitVectorLiteralFactory[UInt]
Used to create a new UInt or cast to UInt
- object UF
- object UFix2D
Two-dimensional
UFix
- object UInt2D extends Serializable
- object UQ
- object UnionElement
- object VHDL extends SpinalMode
- object Verilator
- object Verilog extends SpinalMode
- object WARNING extends AssertNodeSeverity
- object addDefaultGenericValue extends SpinalTag
In VHDL add the generic value in the definition of the blackbox
- object allowAssignmentOverride extends SpinalTag
- object allowDirectionLessIoTag extends SpinalTag
- object allowFloating extends SpinalTag
- object allowOutOfRangeLiterals extends SpinalTag
- object auto extends MemTechnologyKind
- object binaryOneHot extends SpinalEnumEncoding
Binary One hot encoding
Binary One hot encoding
001, 010, 100
Example: - object binarySequential extends SpinalEnumEncoding
Binary Sequential
Binary Sequential
000, 001, 010, 011, 100, 101, ....
Example: - object blackboxAll extends MemBlackboxingPolicy
- object blackboxAllWhatsYouCan extends MemBlackboxingPolicy
- object blackboxByteEnables extends MemBlackboxingPolicy
- object blackboxOnlyIfRequested extends MemBlackboxingPolicy
- object blackboxRequestedAndUninferable extends MemBlackboxingPolicy
- object cloneOf
Return a new data with the same data structure as the given parameter (including bit width)
- object crossClockBuffer extends SpinalTag
- object crossClockDomain extends SpinalTag
- object default
default
statement of a SpinalHDLswitch
/case
default
statement of a SpinalHDLswitch
/case
- See also
- object distributedLut extends MemTechnologyKind
- object doRead extends DuringWritePolicy
- object dontCare extends ReadUnderWritePolicy with DuringWritePolicy
- object dontObfuscate extends SpinalTag
- object dontRead extends DuringWritePolicy
- object eitherFirst extends ReadUnderWritePolicy with DuringWritePolicy
- object getFixRound
- object getFixSym
- object globalCache
- object graySequential extends SpinalEnumEncoding
Gray encoding (sequentially assigned)
Gray encoding (sequentially assigned)
000, 001, 011, 010, ...
- Note
If used in FSM it is not ensured that only gray encoding preserving transitions are done. If that is needed e.g. for CDC reasons, the transitions must be checked manually.
Example: - object ifGen
- object in extends IODirection
Declare an input port
Declare an input port
See IODirection for syntax help.
- object inferred extends SpinalEnumEncoding
Inferred encoding
- object inout extends IODirection
Declare an inout port
Declare an inout port
See IODirection for syntax help.
- object is
is
statement of a SpinalHDLswitch
/case
is
statement of a SpinalHDLswitch
/case
- See also
- object isPow2
Check if a number is a power of 2
- object log2Up
Give number of bit to encode a given number of states
- object native extends SpinalEnumEncoding
Native encoding
- object noBackendCombMerge extends SpinalTag
- object noCombinatorialLoopCheck extends SpinalTag
- object noInit extends SpinalTag
- object noLatchCheck extends SpinalTag
- object noNumericType extends SpinalTag
Transform all unsigned/signed into std_logic_vector
- object out extends IODirection
Declare an output port
Declare an output port
See IODirection for syntax help.
- object ramBlock extends MemTechnologyKind
- object randomBoot extends SpinalTag
- object readFirst extends ReadUnderWritePolicy
- object registerFile extends MemTechnologyKind
- object roundUp
Round up a BigInt
- object signalCache
- object switch
case
/switch
SpinalHDL statementcase
/switch
SpinalHDL statementswitch(x) { is(value1) { // execute when x === value1 } is(value2) { // execute when x === value2 } default { // execute if none of precedent conditions are meet } }
- See also
Example: - object tagAFixResized extends SpinalTag
- object tagAutoResize extends SpinalTag
- object tagTruncated extends SpinalTag
- object uLogic extends SpinalTag
Create a Ulogic tag used by Blackbox in order to transform std_logic into std_ulogic
- object unsetRegIfNoAssignementTag extends SpinalTag
- object unusedTag extends SpinalTag
- object weakCloneOf
Return a new data with the same data structure as the given parameter (except bit width)
- object when
Allow to express SpinalHDL conditional statements based on a
Bool
expression like anif
.Allow to express SpinalHDL conditional statements based on a
Bool
expression like anif
.when(cond1) { myCnt := 0 }elsewhen(cond2) { myCnt := myCnt + 1 }otherwise { myCnt := myCnt - 1 }
- See also
Example: - object widthOf
Return the number of bit of the given data
- object writeFirst extends ReadUnderWritePolicy
Deprecated Value Members
- def Bool: Bool
- Definition Classes
- BoolFactory
- Annotations
- @deprecated
- Deprecated
Use
Bool()
(with braces) instead
- def toSFix(sint: SInt): SFix
- Definition Classes
- SFixCast
- Annotations
- @deprecated
- Deprecated
(Since version ???) Use xxx.toSFix instead
- def toUFix(uint: UInt): UFix
- Definition Classes
- UFixCast
- Annotations
- @deprecated
- Deprecated
(Since version ???) Use xxx.toUFix instead
- object Sel
Sel operation
Sel operation
- Annotations
- @deprecated
- Deprecated
(Since version ???) Use Select instead
- object cloneable
- Annotations
- @deprecated
- Deprecated
(Since version ???) Use HardType instead
- object inWithNull extends IODirection
- Annotations
- @deprecated
- Deprecated
Use apply or port instead: 'val b = in(maybeNull)' or 'val rgb = in port maybeNull'
- object outWithNull extends IODirection
- Annotations
- @deprecated
- Deprecated
Use apply or port instead: 'val b = out(maybeNull)' or 'val rgb = out port maybeNull'
- object wrap
- Annotations
- @deprecated
- Deprecated
(Since version ???) Use HardType instead