Concatenation between two signals

Standard hardware assignment, equivalent to <= in VHDL/Verilog

Automatic connection between two hardware signals or two bundles of the same type.

Direction is inferred by using signal direction (in/out). (Similar behavior to :=)

isNotEqualTo comparison between two SpinalHDL data

isEqualTo comparison between two SpinalHDL data

Use as \= to have the same behavioral as VHDL variable

Allow a signal of an io Bundle to be directionless.

Allow a signal to be overridden.

Allow a register to be partially assigned

Allow a register to have only an init (no assignments)

Cast signal to Bits

Set a signal as inout

Set a data as input

Set a data as output

Set a default value to a signal.

Flip the direction of the signal.

in and out are swapped, inout stay the same.

For a register, get the value it will have at the next clock, as a combinational signal.

Return the width of the data

Get current component with all parents

Create a signal set to 0

Does the base type have initial value

Set initial value of the signal

Is the baseType a node

Is the basetype using reset signal

Is the basetype using soft reset signal

Check if the baseType is vital

Use a SpinalHDL data as a selector for a mux.

Version of SpinalHDL mux that allows Don't Care.

Use a scala.Seq of SpinalHDL data as mux inputs.

Use a scala.Seq of SpinalHDL data as mux inputs.

Version of SpinalHDL muxList that allows Don't Care.

Put the combinatorial logic driving this signal in a separate process

Disable combinatorial loop checking for this Data

Pull a signal to the top level (use for debugging)

Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)

Remove all assignments of the base type

Return a version of the signal which is allowed to be automatically resized where needed.

The resize operation is deferred until the point of assignment later. The resize may widen or truncate, retaining the LSB.

root interface

Set baseType to Combinatorial

Remove the direction (in, out, inout) to a signal

Set baseType to reg

Set baseType to Node

Set the baseType to vital

Recursively set baseType to reg only for output

Generate this if condition is true